Samsung HBM3E now volume shipping to NVIDIA; Micron HBM4 enters qual
Silicon Analysts Weekly for the week of 2026-08-24 to 2026-08-31: Samsung HBM3E now volume shipping to NVIDIA; Micron HBM4 enters qual. A sourced, provenance-marked briefing on AI-chip supply-chain and pricing movements — HBM spot prices, wafer pricing, foundry and CoWoS capacity, per-chip bill-of-materials cost, and HBM qualification status — derived from public data and human-reviewed. Part of the Silicon Analysts semiconductor data layer.
The take
Samsung's HBM3E reaching volume shipping at NVIDIA is the week's clearest supply signal — it widens the qualified supplier base at the exact moment NVIDIA flags 'extreme' memory costs compressing margins. Micron entering HBM4 12-Hi qualification at NVIDIA adds a third horse to the race that matters most for 2027 procurement. Readers tracking GPU market share will find the HBM4 qualification matrix worth pulling this week.
TSMC CoWoS lead time — now 52–78 weeks (was 2026 52-78 wks) (source)
SK Hynix HBM bit share — now ~62% (range: >50% to 70%) (was ~53–55% (range 53–62% across sources)) (source)
TSMC SoIC CoWoS capacity — now SoIC capacity ~4k wpm in 2024 growing to ~8k wpm in 2025, implying ~90% CAGR 2022–2027 (was 10K wafers/month expanding to 50K wafers/month in 2027) (source)
TSMC CoWoS capacity — ~80,000–140,000 wafers per month by end-2025/2026, growing at ~80% CAGR (2022–2027)… (source)
TSMC SoIC ramp — now 10,000 to 50,000 wafers per month by 2027 (was Q4 2026 CAGR of 100% through 2026; eight-fold from 2023 levels by end of 2026) (source)
Nvidia Warns 'Extreme' Memory Costs, Projects 70% FY2028 Revenue Growth Constrained by Supply — Nvidia's gross margin compression from 'extreme' memory pricing and supply-constrained guidance reveals critical HBM/DRAM bottlenecks persisting through 2028. This signals sustained pricing power for memory suppliers but warns of systemic supply chain stress that could impede AI infrastructure rollout if not resolved. (Business Insider) · _In our data:_ NVIDIA — 15 developments tracked this quarter · NVIDIA storyline · HBM price by generation · HBM market share by vendor
TSMC CapEx Raised to $60B for 2026: AI Buildout Drives Fab Expansion — TSMC's CapEx increase from $55-60B reflects foundry's aggressive response to AI-driven demand for larger HPC dies requiring CoWoS multi-die packaging and expanded cleanroom footprint. Signals sustained semiconductor equipment demand and supply chain investment, benefiting ASML and packaging suppliers. (BigGo Finance) · _In our data:_ TSMC — 7 developments tracked this quarter · TSMC storyline · CoWoS packaging capacity · AI accelerator manufacturing cost
SK Hynix Indiana Fab Groundbreaking Signals Major US Memory Capacity Expansion — SK Hynix's Indiana facility groundbreaking represents critical new memory supply capacity for the US market, directly addressing acute HBM and DRAM shortages constraining AI chip deployment. This geographically diversified production will reduce Korea/Taiwan supply chain concentration risk and improve lead times for US-based AI infrastructure buyers. (SK Hynix Newsroom) · _In our data:_ SK Hynix — 16 developments tracked this quarter · SK Hynix storyline · HBM price by generation · HBM market share by vendor
HBM watch
Micron × NVIDIA (HBM4 12-Hi): now In qualification — NVIDIA is scaling toward 12-Hi HBM4 production; Samsung, SK Hynix, and Micron are all active against tighter technical requirements. (source · timeline)
The Nine-Month ASIC: How Jalapeño Rewrites the Economics of Custom Silicon Development — OpenAI's Jalapeño inference ASIC completed tape-out in nine months — a cycle time that challenges every assumption about ASIC development economics. This analysis unpacks the NRE cost structure, reticle utilization tradeoffs, and time-to-market dynamics reshaping the hyperscaler silicon playbook.
mi325x packaging_cost — was 500 → now 1300 (Model restatement, not market movement: packaging cost was below the published floor of both constituent technologies (corrected in the cost)
mi325x est_mfg_cost — was 5950 → now 6750 (Moved with the packaging restatement (500 -> 1300); logic, HBM, and test/assembly unchanged. A basis change of the cost model reaching the D)
Citation & licensing. Figures from this issue are free to cite — in articles, research, internal decks, and AI-generated answers — with attribution to Silicon Analysts and a link to this page. Commercial redistribution and derived data products require a license. See the Citation & Data License.
Get the next issue in your inbox
One short, sourced email a week on the AI-chip supply chain — only when the data moves.
One short email a week — only when the data moves. No marketing, ever. One-click unsubscribe.