Chip Cost Calculator — GDPW, Net Die Yield & Wafer Cost Model
Calculate Gross Dies Per Wafer (GDPW) and net die yield for any chip design. Enter die dimensions and wafer size to see how many good dies per wafer, factoring in edge exclusion, flat/notch losses, and defect density. Supports TSMC N3, N5, N4, Samsung, Intel, and GlobalFoundries nodes from 180nm to 2nm. Includes wafer procurement cost, scribe line loss, Poisson and Murphy yield models, advanced packaging costs (CoWoS, EMIB, SoIC), HBM memory pricing, and margin analysis. Free alternative to paid die calculators — no subscription or signup required.
GDPW & Net Die Calculator
Calculate Gross Dies Per Wafer (GDPW) and net die yield for any chip design. Enter your die dimensions and wafer size to instantly see how many good dies you can expect per wafer, factoring in edge exclusion, flat/notch losses, and defect density.
How GDPW Is Calculated
Gross Dies Per Wafer estimates the maximum number of rectangular dies that fit on a circular wafer. The standard formula accounts for wafer diameter (typically 300mm), die area (X × Y mm), and edge exclusion zones. Our calculator extends this with Murphy’s yield model to give you net good dies — the number you can actually sell after accounting for defect density.
Free Alternative to Paid Die Calculators
Silicon Analysts’ chip cost calculator provides GDPW, net die yield, and full chip cost modeling — including wafer costs, advanced packaging (CoWoS, EMIB), and HBM memory pricing — completely free. No subscription required. Model costs from 28nm through 2nm with real-time parameter adjustments.
Looking for a comprehensive reference? Read our guide: How Many Chips Fit on a Wafer →
Semiconductor Chip Cost FAQ
- How many chips fit on a 300mm wafer?
- The number of chips per wafer depends on die size. A small IoT chip (5×5mm) yields ~2,800 gross dies per 300mm wafer. A smartphone SoC (10×12mm) yields ~580. A large GPU die like the NVIDIA H100 (26×31mm, 814mm²) yields ~80 gross dies. After accounting for edge losses and defect-driven yield, net good dies are typically 60–95% of gross, depending on process maturity.
- What is GDPW in semiconductor manufacturing?
- GDPW (Gross Dies Per Wafer) is the theoretical maximum number of rectangular dies that can be cut from a circular silicon wafer. It’s calculated based on wafer diameter, die dimensions, and edge exclusion zones. GDPW is the starting point for chip cost modeling — higher GDPW means lower cost per die. Our calculator computes GDPW automatically from your die dimensions.
- How do you calculate die yield?
- Die yield is calculated using defect density models (Murphy’s, Poisson, or negative binomial). The key inputs are defect density (defects/cm²) and die area. Larger dies have lower yield because they’re more likely to contain a defect. At 3nm, a typical 300mm² GPU die might achieve 60–75% yield, while a small 50mm² die could achieve 90%+.
- How much does a silicon wafer cost?
- Silicon wafer processing costs depend on process node: ~$3,000 for 28nm, ~$8,000 for 7nm, ~$16,000–18,000 for 5nm, ~$20,000–22,000 for 3nm, and ~$28,000–30,000 estimated for 2nm. These are wafer processing costs at TSMC, not blank wafer costs (blank 300mm wafers are ~$100–150 each).
- How much does it cost to manufacture a semiconductor chip?
- Chip manufacturing cost depends on process node, die size, wafer price, yield, and packaging. A small IoT chip on a mature 28nm node may cost $2–5, while an advanced AI accelerator on TSMC N3 can cost $2,000–10,000+ per die. Use our free calculator to model costs for any configuration.
- What is the cost breakdown of an NVIDIA H100?
- The estimated manufacturing cost of an NVIDIA H100 SXM5 GPU is approximately $3,320, broken down as: ~$2,100 for the 4nm logic die (814mm² on TSMC N4), ~$480 for six HBM3 stacks (80GB total), ~$400 for CoWoS-S packaging, and ~$200 for test and assembly. NVIDIA sells the H100 at approximately $28,000, implying a gross margin of roughly 88%.
- How much does a TSMC wafer cost in 2026?
- TSMC wafer costs in 2026 range from approximately $3,000 for mature nodes (28nm) to $19,500 for 3nm (N3/N3E) processes. The 5nm (N5) node costs approximately $18,500 per wafer. These estimates include standard process fees but exclude mask costs, which can add $10–20M for advanced EUV nodes.
- Why are chip costs increasing despite Moore's Law?
- While transistor density continues to improve, the cost per transistor stopped decreasing at the 5nm node. Three factors drive this: (1) EUV lithography requires more expensive equipment and more patterning passes, (2) advanced packaging (CoWoS, HBM integration) adds significant cost layers that didn't exist at older nodes, and (3) wafer costs at sub-5nm have increased 30–50% per node transition due to process complexity.