How Many Chips Fit on a Wafer?
The number of chips per wafer is the single biggest driver of semiconductor manufacturing cost. A small IoT chip yields thousands of dies per 300mm wafer, while a massive AI accelerator die like the NVIDIA H100 yields fewer than 80. Here’s how to calculate it and why it matters.
Quick Reference: Dies Per Wafer by Chip Type
| Chip Type | Die Size (mm²) | Process Node | GDPW (300mm) | Est. Yield | Net Good Dies |
|---|---|---|---|---|---|
| Small IoT MCU | 25 (5×5) | 28nm | ~2,800 | ~95% | ~2,660 |
| Smartphone SoC | 120 (10×12) | 4nm | ~580 | ~85% | ~493 |
| Laptop CPU | 200 (13×15) | 5nm | ~340 | ~80% | ~272 |
| NVIDIA H100 GPU | 814 (26×31) | 4nm | ~80 | ~65% | ~52 |
| Apple M4 Ultra | ~400 (20×20) | 3nm | ~160 | ~72% | ~115 |
| AMD MI300X (chiplet) | ~200 | 5nm | ~340 | ~80% | ~272 |
GDPW values assume 300mm wafer with 3mm edge exclusion. Yields are estimates based on published defect density data for each node’s maturity level.
The GDPW Formula
GDPW = (π × (D/2 − E)²) / S − (π × (D/2 − E)) / √(2 × S)
Where:
- D = wafer diameter (300mm for modern fabs)
- E = edge exclusion zone (typically 2–3mm)
- S = die area (width × height in mm²)
The first term estimates how many rectangles fit in the usable circular area. The second term subtracts partial dies lost along the wafer edge. This is an approximation — actual die placement uses stepping algorithms that can recover a few extra dies depending on die aspect ratio and orientation.
Why Die Size Matters So Much for Cost
Die size has a non-linear impact on chip cost. Doubling die area does not simply double cost — it more than doubles it, for two compounding reasons:
- Fewer dies per wafer: On a circular wafer, doubling the rectangular die area yields less than half the number of dies due to edge losses.
- Lower yield: Larger dies are more likely to contain a killer defect. Yield drops exponentially with die area at any given defect density.
This is precisely why the semiconductor industry is moving toward chiplet architectures — multiple small dies connected via advanced packaging (CoWoS, EMIB, UCIe) instead of one monolithic die. AMD’s MI300X uses this approach: multiple ~200mm² chiplets instead of a single 800mm²+ die, dramatically improving yield and cost.
Yield: Why You Don’t Get All the Dies
GDPW tells you how many dies physically fit on a wafer. But not all of them work. Defects introduced during fabrication — particles, lithography errors, implant variations — kill some fraction of dies. The percentage that pass testing is called die yield.
Yield is typically modeled using Murphy’s model or the Poisson model. The key inputs are:
- Defect density (D0): Typically 0.05–0.15 defects/cm² for mature nodes, 0.2–0.5 for leading edge
- Die area (A): Larger dies catch more defects
At TSMC’s 3nm node, a small 50mm² die might achieve 90%+ yield, while an 800mm² GPU die could see yields below 50% in early production. This yield gap is the main reason large AI accelerator dies are so expensive per unit.
How AI Chips Changed the Economics
The NVIDIA H100’s 814mm² die pushed the limits of what’s economically viable on a single monolithic chip. At ~80 gross dies per wafer and an estimated 60–70% yield, each wafer produces only ~50 good H100 dies. With TSMC N4 wafers costing ~$16,000+, the die cost alone exceeds $300 — before packaging, HBM memory, and test.
NVIDIA’s Blackwell B200 moved to a dual-die architecture to address this: two smaller dies connected via NVLink, improving yield while delivering more compute. This chiplet trend is now standard across the industry for high-performance AI accelerators.
Try It Yourself
Enter your die dimensions and process node to calculate GDPW, yield, and full chip cost with our free interactive calculator.
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Chips Per Wafer FAQ
- How many chips fit on a 300mm wafer?
- It depends on die size. A small IoT chip (5×5mm, 25mm²) yields ~2,800 gross dies. A smartphone SoC (10×12mm, 120mm²) yields ~580. A laptop CPU (13×15mm, 200mm²) yields ~340. A large GPU like the NVIDIA H100 (26×31mm, 814mm²) yields only ~80 gross dies. Net good dies after yield losses are typically 60–95% of gross.
- What is GDPW (Gross Dies Per Wafer)?
- GDPW is the theoretical maximum number of rectangular dies that can be cut from a circular silicon wafer. The formula accounts for wafer diameter (typically 300mm), die area (width × height), and edge exclusion zones (2–3mm). GDPW is the starting point for all chip cost calculations.
- How is die yield calculated?
- Die yield is calculated using defect density models such as Murphy’s, Poisson, or negative binomial. The key inputs are defect density (defects/cm²) and die area (cm²). Larger dies have lower yield because they are more likely to contain a killer defect. Typical yields range from 95% for small mature-node chips to below 50% for very large leading-edge dies.
- Why does doubling die size more than double chip cost?
- Doubling die area has two compounding effects: (1) you get fewer than half the gross dies per wafer due to the circular wafer geometry, and (2) yield drops non-linearly because larger dies are more likely to contain defects. A 400mm² die can cost 3–4x as much per good die as a 200mm² die on the same process.
- What is the GDPW formula?
- The standard GDPW formula is: GDPW = (π × (D/2 − E)²) / S − (π × (D/2 − E)) / √(2 × S), where D = wafer diameter (300mm), E = edge exclusion (2–3mm), and S = die area (width × height in mm²). This approximation accounts for the inefficiency of packing rectangles on a circle.