How much does an MPW shuttle cost?

MPW (Multi-Project Wafer) shuttle costs range from $5,000 to $100,000+ depending on process node, die area, and provider. A 65nm shuttle slot for a small die (~4mm²) might cost $5,000–$15,000, while a 28nm slot costs $20,000–$50,000, and a 7nm slot can exceed $100,000. You share the mask set with other designs, which dramatically reduces NRE compared to a full mask set.

How much does a full mask set cost?

Full mask set costs range from approximately $100,000 at 180nm to $10–$20 million at 3nm. The cost increases at each node due to the number of mask layers and multi-patterning requirements. At 28nm, expect $800K–$1.5M. At 7nm with EUV, expect $3–$5M. At 5nm, expect $5–$8M. At 3nm, expect $10–$20M.

How long does it take to go from design to silicon?

For an MPW run: 8–20 months total (3–12 months design + 3–6 months fabrication + 1–2 months test/packaging). For production: 12–24 months from tape-out to volume production, plus design time. Advanced nodes (3nm, 5nm) tend toward the longer end due to complex verification requirements and longer fab cycle times.

What is the minimum order for TSMC?

TSMC’s minimum engagement varies by node and relationship. For MPW shuttles (CyberShuttle), there is no minimum wafer commitment — you buy a die allocation on a shared mask. For production, typical minimums are 1,000+ wafer starts per year for direct engagement at advanced nodes. Intermediaries (VCAs) can aggregate smaller orders, sometimes as low as 25 wafers.

What is a PDK and why do I need one?

A PDK (Process Design Kit) is a set of files provided by the foundry containing device models (SPICE), design rules (DRC/LVS decks), technology files, and standard cell libraries specific to a process node. You cannot design a chip without the PDK — it defines the physical and electrical constraints your design must meet. PDK access typically requires an NDA with the foundry.

Should I use an intermediary or go direct to the foundry?

Use an intermediary (VCA) if your annual wafer volume is below 1,000 wafers, if you’re at a mature node (28nm+), or if you don’t have in-house foundry management expertise. Go direct if you need advanced nodes, high volume, or process customization. Intermediaries add 10–30% to wafer costs but handle NDAs, PDK logistics, DRC, tape-out, and often packaging and test.

What EDA tools do I need for chip design?

The three major EDA vendors are Cadence, Synopsys, and Siemens (Mentor). A full digital design flow typically requires synthesis, place-and-route, static timing analysis, and physical verification (DRC/LVS) tools. Annual EDA licenses for a small team cost $200K–$500K. For advanced nodes (7nm and below), you may need specialized tools for multi-patterning and EUV-aware DRC, which increases costs.

What is the difference between 28nm and 7nm for chip design?

28nm is the last major planar CMOS node — it has excellent foundry availability, mature yields, and moderate costs (~$3,000/wafer, ~$800K–$1.5M mask set). 7nm introduces FinFET transistors and EUV lithography, offering 3–4× the transistor density but at much higher cost (~$9,500/wafer, $3–$5M mask set). For most IoT, automotive, and industrial chips, 28nm is the cost-optimal choice. 7nm and below are typically reserved for high-performance computing, AI, and mobile SoCs.

Foundry Engagement Guide: From MPW Shuttle to Production

Getting silicon fabricated is the most complex and expensive step in building a chip. Whether you’re a startup doing your first MPW shuttle run or an established company scaling to production wafers, the foundry engagement process involves navigating NDAs, PDK access, design rule compliance, mask creation, and wafer ordering — each with its own costs, timelines, and pitfalls. This guide walks through the entire process from first contact to production ramp, with real cost data and interactive tools to model your specific scenario.

Last updated: February 2026 · Data sources: Industry estimates, TSMC/Samsung public filings, foundry pricing trackers · Model your tape-out budget →

Quick answer: There are three paths to silicon: MPW shuttles ($5K–$100K, share a mask with other designs), VCA intermediaries ($50K–$500K, turnkey service through a broker), or direct foundry engagement ($500K–$15M+ NRE, lowest per-wafer cost at volume). The full process from NDA to packaged silicon takes 8–20 months for prototypes or 12–24 months for production.

Foundry Engagement Models — Which Path Is Right for You?

Before you write a single line of RTL, you need to decide how you’ll access a foundry. The choice depends on your volume, budget, timeline, and in-house expertise.

MPW Shuttle (Multi-Project Wafer)

Share a mask set with other designs. You get a small allocation of dies on a shared wafer — typically 10–200 packaged dies depending on die size and shuttle program.

Best for: Prototypes, proof-of-concept, academic projects, very early-stage startups
Cost: $5K–$100K depending on node and die area (vs $500K–$15M+ for full mask sets)
Providers: MOSIS (US), Europractice (EU), CMC Microsystems (Canada), TSMC CyberShuttle, Samsung MPW
Timeline: 3–6 months from tape-out to die delivery
Pros: Lowest NRE cost, access to advanced nodes without committing to full production
Cons: Fixed schedules (shuttles run quarterly or less), limited die quantity, no process customization

VCA / Intermediary (Value Chain Aggregator)

Work through a broker or intermediary who handles foundry logistics on your behalf. They manage the NDA, PDK access, DRC signoff, tape-out submission, and often packaging and test.

Best for: Small-to-mid companies without direct foundry relationships
Cost: 10–30% premium over direct pricing, but lower total cost when factoring staff/time savings
Providers: MOSIS, Europractice, various design service companies
Pros: Turnkey service, lower internal headcount requirement, access to nodes you couldn’t get directly
Cons: Less control over scheduling, potential IP sensitivity concerns, higher per-wafer cost

Direct Foundry Engagement

Work directly with TSMC, Samsung, Intel Foundry Services, GlobalFoundries, or other fabs. This gives you the most control and the lowest per-wafer cost at volume.

Best for: Companies with production volume commitments and advanced node requirements
Cost: Full mask set ($800K at 28nm → $5–8M at 5nm → $10–20M at 3nm), but lowest per-wafer cost at volume
Requirements: Typically need annual wafer volume >1,000 wafers for direct engagement at TSMC
Pros: Full process customization, priority scheduling, direct engineering support
Cons: Significant volume commitments, long qualification process, high NRE

Engagement Model Comparison

Factor	MPW Shuttle	VCA / Intermediary	Direct Foundry
NRE Cost	$5K–$100K	$50K–$500K	$500K–$15M+
Per-Wafer Cost	N/A (die-level)	$3K–$22K+	$2.5K–$20K
Min. Volume	1 shuttle slot	1–25 wafers	100–1,000+ wafers
Timeline	3–6 months	4–8 months	6–18 months
Process Nodes	Select nodes only	Most nodes	All nodes
Engineering Support	Minimal	Moderate	Full
Best For	Prototype	Low-volume prod.	High-volume prod.

Model your full tape-out budget across all three engagement models →

Choosing a Process Node

Process node selection is one of the most consequential decisions in chip design. It determines your wafer cost, mask cost, design complexity, foundry availability, and time to market. The table below shows cost data from our platform’s foundry pricing tracker.

Node	Technology	Typical Applications	Est. Mask Cost	Wafer Cost
180nm	Planar CMOS	Analog, power management, sensors	~$100K	~$1,500
130nm	Planar CMOS	Mixed-signal, RFID, IoT	~$150K	~$1,800
65nm	Planar CMOS	IoT SoCs, RISC-V cores	$300K–$500K	~$2,500
40nm	Planar CMOS	MCUs, connectivity chips	$500K–$800K	~$3,000
28nm	Planar CMOS	Last planar node — excellent cost/perf	$800K–$1.5M	$3,000
16nm/12nm	FinFET	First FinFET, high-perf digital	$2M–$3M	$4,500
7nm	FinFET + EUV	AI inference, 5G, HPC	$3M–$5M	$9,500
5nm	FinFET + EUV	Data center AI, mobile AP	$5M–$8M	$18,500
3nm	GAA (GAAFET)	Leading-edge AI, mobile flagship	$10M–$20M	$19,500

Wafer costs from Silicon Analysts foundry pricing tracker (TSMC reference pricing). Mask costs are industry estimates. Samsung 3nm and 5nm wafer costs are approximately 20–25% lower than TSMC equivalents. Full wafer pricing reference →

Node selection guidance: If your design can work at 28nm, seriously consider staying there. It is the last planar CMOS node with excellent foundry availability (TSMC, Samsung, UMC, GlobalFoundries, SMIC), mature yields, and reasonable costs. The jump to FinFET (16nm/7nm) triples wafer cost and increases mask cost by 3–5×. Reserve 7nm and below for designs that genuinely need the transistor density — AI/ML training chips, high-performance mobile SoCs, or products where die area reduction justifies the NRE premium.

Compare wafer costs across all process nodes interactively →

The Engagement Process Step by Step

Regardless of which engagement model you choose, the path from concept to packaged silicon follows the same fundamental phases. Timelines vary by node and complexity.

NDA & PDK → Technology Selection → Design & Verification → Tape-out & Masks → Wafer Fab → Package & Test → Production Ramp

[2–4 wk] [2–8 wk] [3–12 mo] [4–8 wk] [8–16 wk] [4–8 wk] [ongoing]

Total: 8–20 months (MPW prototype) | 12–24 months (production)

Phase 1: Initial Contact & NDA (2–4 weeks)

Your first interaction with a foundry (or intermediary) starts with a mutual NDA. Before sharing any process specifications, pricing, or design rules, the foundry needs legal protection for their IP — and you need protection for yours.

Prepare a high-level design brief: target process node, estimated die area, annual volume projection, and timeline
NDA covers process specs, pricing, design rules, and yield data — typically 3–5 years duration
For intermediaries (VCA), the NDA may cover a broader portfolio of foundry nodes
Most foundries will not share detailed pricing or PDK access without a signed NDA

Phase 2: Technology Selection & PDK Access (2–8 weeks)

Once the NDA is in place, you gain access to the foundry’s Process Design Kit (PDK) and Design Rule Manual (DRM). This is where you make critical technology decisions.

PDK contents: SPICE device models, DRC/LVS rule decks, technology files, standard cell libraries, IO libraries
Process options: Number of metal layers (6–15+), analog/RF options, high-voltage options, embedded memory
EDA tools required: Cadence Virtuoso (analog), Synopsys Design Compiler + IC Compiler (digital), Calibre/PVS (verification)
EDA licensing costs: $200K–$500K/year for a small team; $500K–$1M+ for full digital flow at advanced nodes
PDK access may require a signed technology license agreement (TLA) in addition to the NDA

Phase 3: Design & Verification (3–12+ months)

This is your work, not the foundry’s. But foundry touchpoints are critical throughout:

DRC (Design Rule Check): Your layout must pass the foundry’s DRC deck — a single violation means tape-out rejection
LVS (Layout vs. Schematic): Verifies your physical layout matches the intended circuit
ERC (Electrical Rule Check): Catches electrical violations (antenna effects, latch-up risks)
IR drop & electromigration analysis: Ensures power delivery is robust at target frequency
Some foundries offer pre-tape-out design review services (especially for first-time customers)
Allow 4–6 weeks for final verification closure — this is where most schedule slips occur

Phase 4: Tape-Out & Mask Making (4–8 weeks)

Tape-out is the point of no return. Your design is finalized, submitted as GDSII or OASIS format, and the foundry begins manufacturing the mask set.

GDSII/OASIS file submission to foundry — typically through a secure file transfer portal
Foundry runs incoming quality checks (DRC re-verification, fill pattern insertion)
Mask writing and inspection: 2–4 weeks for mature nodes, 4–8 weeks for advanced EUV nodes
At 7nm and below, multi-patterning increases the number of masks from ~40 to 80+, driving mask costs from $3M to $10M+
For MPW shuttles, your design is combined with others onto the shared mask — no scheduling flexibility

Phase 5: Wafer Fabrication (8–16 weeks)

The foundry processes your wafers through hundreds of sequential steps. Cycle time depends on node complexity.

Fab cycle time: ~8 weeks at 28nm, ~10–12 weeks at 7nm, ~14–16 weeks at 3nm
Standard lot size: 25 wafers (300mm) per lot
Test wafer options available for process characterization (additional cost)
Foundry provides yield monitoring data during fabrication
At TSMC, capacity must be reserved 6–12 months ahead for production lots — miss the window and you wait

Phase 6: Wafer Test, Dicing & Packaging (4–8 weeks)

After fabrication, wafers go through probe testing, dicing, and packaging. For advanced AI chips, packaging can be the most expensive and constrained step.

Wafer probe testing identifies good dies before dicing — generates a wafer map
Dicing: laser or mechanical cutting of individual dies from the wafer
Packaging costs range from $0.80 (QFN) to $120+ (3D SoIC) per unit
Advanced packaging (CoWoS, EMIB) has its own capacity constraints — lead times of 40–52 weeks at TSMC as of early 2026
Final test (FT) validates packaged devices against the full specification

Estimate packaging costs for your chip →

Phase 7: Production Ramp (if applicable)

If first silicon is successful, the transition to production involves qualification, yield optimization, and volume pricing negotiations.

Engineering samples (ES) → customer qualification samples (QS) → production
Typical yield improvement: 10–20 percentage points from first silicon to mature production
Volume pricing discounts typically available at 500+ wafers/year
Budget for at least one re-spin — first silicon rarely meets all specs

Cost Breakdown — Where Your Money Goes

Chip development costs split into two categories: non-recurring engineering (NRE), which you pay once regardless of volume, and recurring costs that scale with production.

Non-Recurring Engineering (NRE) Costs

Cost Category	28nm Example	5nm Example
Mask set	$800K–$1.5M	$5M–$8M
EDA tools (annual license)	$200K–$500K	$500K–$1M+
IP licensing (ARM core, PHYs, etc.)	$100K–$1M+	$500K–$5M+
Design services (if outsourced)	$200K–$1M	$1M–$5M+
Packaging development	$50K–$200K	$200K–$1M+
Test program development	$50K–$200K	$100K–$500K
Total NRE	$1.4M–$3.4M	$7.3M–$20.5M+

Recurring (Per-Unit) Costs

Cost Category	28nm (10mm² die)	5nm (100mm² die)
Wafer cost	$3,000	$18,500
Gross dies per wafer	~6,500	~640
Estimated yield	~95%	~88%
Cost per good die	~$0.49	~$33
Packaging (FC-BGA / CoWoS)	$0.80–$8	$8–$70+
Test	$0.10–$1	$0.50–$5
Total per unit	$1.40–$9.50	$41–$108+

Wafer costs from Silicon Analysts foundry pricing data. Die counts calculated using the GDPW formula.

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Foundry Comparison

The foundry you choose affects your cost, timeline, and available process nodes. Here’s how the major foundries compare for different use cases.

TSMC

The dominant foundry for leading-edge nodes (3nm, 5nm, 7nm) with the widest IP ecosystem and highest yields. Also strong at mature nodes (28nm, 40nm) through specialty technology platforms. MPW access via the CyberShuttle program. Best for AI chips, mobile SoCs, and HPC. Annual capacity: ~800K wafers at 3nm, ~1.5M at 5nm, ~5M at 28nm.

3nm wafer: ~$19,500 (range $17K–$22K)
5nm wafer: ~$18,500 (range $16K–$21.3K)
7nm wafer: ~$9,500 (range $8.1K–$10.9K)
28nm wafer: ~$3,000 (range $2.55K–$3.45K)

Samsung Foundry

Competes at 3nm with gate-all-around (GAA) transistors and offers 20–25% lower wafer pricing than TSMC to win customers. MPW available. Best for cost-sensitive designs or companies wanting an alternative to TSMC.

3nm wafer: ~$15,000 (range $13K–$17K)
5nm wafer: ~$13,000 (range $11K–$15K)

GlobalFoundries

Exited the leading-edge race to focus on specialty nodes (12nm–180nm). Offers FD-SOI technology (22FDX) as a unique differentiator for ultra-low-power applications. More accessible for smaller companies than TSMC or Samsung. Best for IoT, automotive, RF, and mixed-signal designs.

Intel Foundry Services (IFS)

Building out its foundry business with aggressive pricing and government subsidies (CHIPS Act funding). Offers advanced packaging (EMIB, Foveros). Best for companies wanting US-based manufacturing or access to Intel-specific IP.

UMC, SMIC & Others

UMC: Mature nodes (28nm+), reliable and cost-effective. SMIC: Chinese foundry, limited by US export controls, capable up to ~7nm-equivalent. Tower Semiconductor: Specialty analog, power management, and RF.

Explore 100+ fabs worldwide with capacity data →

Common Pitfalls & How to Avoid Them

Underestimating EDA costs. Synopsys/Cadence/Siemens licenses can cost more than the wafers themselves. Budget $200K–$1M/year for a small-to-mid design team. Open-source EDA (OpenROAD, Yosys) is maturing but is not yet production-ready for advanced nodes.
Missing DRC rules. A single DRC violation means your tape-out gets rejected. Allow 4–6 weeks for final physical verification closure. Run DRC incrementally, not just at the end.
IP integration surprises. Licensed IP blocks (ARM cores, Synopsys PHYs, memory compilers) may need process-specific customization and have their own qualification timelines. Start IP procurement early.
Yield underestimation. First silicon yield at advanced nodes is typically 30–60%. Budget for lower yield than your models predict and plan for at least one re-spin ($1M+ per re-spin at 7nm and below).
Packaging as an afterthought. Advanced packaging (CoWoS, EMIB) has its own capacity constraints and 3–6 month lead times. Reserve packaging slots when you reserve fab capacity.
Not reserving fab capacity early enough. At TSMC, capacity must be reserved 6–12 months ahead for production lots. During peak demand periods, even shuttle slots can fill up months in advance.
Insufficient test coverage. A poor test program misses defective dies, leading to field failures and customer returns. Invest in design-for-test (DFT) early in the design process.

Interactive Cost Modeling Tools

Use our free tools to model specific foundry engagement scenarios:

Related Resources

Foundry Engagement FAQ

How much does an MPW shuttle cost?: MPW (Multi-Project Wafer) shuttle costs range from $5,000 to $100,000+ depending on process node, die area, and provider. A 65nm shuttle slot for a small die (~4mm²) might cost $5,000–$15,000, while a 28nm slot costs $20,000–$50,000, and a 7nm slot can exceed $100,000. You share the mask set with other designs, which dramatically reduces NRE compared to a full mask set.
How much does a full mask set cost?: Full mask set costs range from approximately $100,000 at 180nm to $10–$20 million at 3nm. The cost increases at each node due to the number of mask layers and multi-patterning requirements. At 28nm, expect $800K–$1.5M. At 7nm with EUV, expect $3–$5M. At 5nm, expect $5–$8M. At 3nm, expect $10–$20M.
How long does it take to go from design to silicon?: For an MPW run: 8–20 months total (3–12 months design + 3–6 months fabrication + 1–2 months test/packaging). For production: 12–24 months from tape-out to volume production, plus design time. Advanced nodes (3nm, 5nm) tend toward the longer end due to complex verification requirements and longer fab cycle times.
What is the minimum order for TSMC?: TSMC’s minimum engagement varies by node and relationship. For MPW shuttles (CyberShuttle), there is no minimum wafer commitment — you buy a die allocation on a shared mask. For production, typical minimums are 1,000+ wafer starts per year for direct engagement at advanced nodes. Intermediaries (VCAs) can aggregate smaller orders, sometimes as low as 25 wafers.
What is a PDK and why do I need one?: A PDK (Process Design Kit) is a set of files provided by the foundry containing device models (SPICE), design rules (DRC/LVS decks), technology files, and standard cell libraries specific to a process node. You cannot design a chip without the PDK — it defines the physical and electrical constraints your design must meet. PDK access typically requires an NDA with the foundry.
Should I use an intermediary or go direct to the foundry?: Use an intermediary (VCA) if your annual wafer volume is below 1,000 wafers, if you’re at a mature node (28nm+), or if you don’t have in-house foundry management expertise. Go direct if you need advanced nodes, high volume, or process customization. Intermediaries add 10–30% to wafer costs but handle NDAs, PDK logistics, DRC, tape-out, and often packaging and test.
What EDA tools do I need for chip design?: The three major EDA vendors are Cadence, Synopsys, and Siemens (Mentor). A full digital design flow typically requires synthesis, place-and-route, static timing analysis, and physical verification (DRC/LVS) tools. Annual EDA licenses for a small team cost $200K–$500K. For advanced nodes (7nm and below), you may need specialized tools for multi-patterning and EUV-aware DRC, which increases costs.
What is the difference between 28nm and 7nm for chip design?: 28nm is the last major planar CMOS node — it has excellent foundry availability, mature yields, and moderate costs (~$3,000/wafer, ~$800K–$1.5M mask set). 7nm introduces FinFET transistors and EUV lithography, offering 3–4× the transistor density but at much higher cost (~$9,500/wafer, $3–$5M mask set). For most IoT, automotive, and industrial chips, 28nm is the cost-optimal choice. 7nm and below are typically reserved for high-performance computing, AI, and mobile SoCs.