How much does your chip cost to manufacture?
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HBM market dynamics — accelerator specs, vendor market share, spot pricing, supply chain signals, and revenue forecasts.
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Explore 64 semiconductor fabs from TSMC, Samsung, Intel, GlobalFoundries, SMIC, UMC, and more. Filter by node, country, and capacity.
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Historical time series for wafer pricing, HBM/DRAM costs, fab utilization, CoWoS capacity, and NRE trends — 306 sourced data points across 16 datasets.
Cost Bridge Chart
Side-by-side manufacturing cost comparison across logic die, HBM memory, packaging, and assembly for 13 AI accelerators.
Packaging Model
Compare CoWoS-S, CoWoS-L, EMIB, SoIC, and flip-chip architectures with HBM stack cost analysis.
Supply Chain Explorer
Interactive sunburst visualization of semiconductor supply chain chokepoints — from ASML to Zeiss optics to Japanese photoresist monopolies.
Price / Performance Frontier
Compare AI accelerators on cost, throughput, training time, and TCO — H100, B200, MI300X, TPU v5p, and more.
Allocation Dashboard
Track foundry allocation status, CoWoS packaging availability, and HBM supply signals across 14 process nodes from TSMC, Samsung, Intel, and more.
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Guided 5-step workflow for fabless teams evaluating tapeout decisions — chip definition, foundry selection, cost modeling, competitive benchmarking, and go/no-go summary.
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Latest Analysis & Market Intelligence
Deep-dive reports and daily AI-detected supply-chain signals — each sourced and dated. Public sources only.
SK Hynix Commits $5.8B to Advanced HBM Packaging Facility; TSMC Confirms 2027 Wafer Price Hikes Up to 10%
SK Hynix's board has approved KRW 7.09 trillion ($5.8 billion) in capital expenditure for a next-generation advanced packaging facility in Cheongju, directly targeting HBM packaging capacity expansion to meet accelerating AI accelerator demand. Concurrently, TSMC has confirmed wafer manufacturing price increases for 2027, with mature-node technologies (12nm, 16nm, 28nm) facing hikes of up to 10%, signaling broad-based foundry cost inflation that will flow through to AI hardware BOMs.
SK Hynix packaging CapEx: +$5.8B committed; TSMC mature-node wafer price hike: up to +10% effective 2027; advanced-node pricing direction unquantified but directionally upward per Barchart/TSMC guidance.
China Eyes Export Controls on AI Chips & Models; AMD Helios Rack Enters Market with Azure Deal
China's Ministry of Commerce is actively consulting with domestic AI firms on tighter export controls covering AI model weights, chip designs, and potential restrictions on overseas foundries—including TSMC and Qualcomm—from producing advanced semiconductors based on Chinese IP, per a Financial Times report cited by Reuters. Simultaneously, AMD has formally launched its Helios rack-scale AI system powered by MI455X GPUs, with Microsoft Azure confirmed as a new deployment customer for H2 2026, introducing a credible rack-level competitive alternative to Nvidia's CoWoS-packaged accelerator dominance.
Geopolitical: Potential restriction on TSMC fab access for Chinese-designed advanced chips (scope/timing unquantified); AMD Helios: Azure H2 2026 deployment commitment (unit volume undisclosed).
TSMC Commits $100B+ Arizona Expansion, Accelerates 3nm Conversion to Meet AI Chip Surge
TSMC has announced an additional $100 billion investment in its Arizona facilities — part of a broader $265 billion U.S. commitment — and confirmed it is actively converting 5nm capacity to 3nm to meet surging AI chip demand, with CFO Wendell Huang citing a 'strong, multi-year demand mega trend.' Separately, Bloomberg analysis of Moonshot AI's Kimi K3 model highlights that efficiency-optimized AI architectures continue to require large memory footprints, reinforcing sustained structural demand for HBM from suppliers including SK Hynix.
Capacity: TSMC U.S. CapEx raised by +$100B incremental; total U.S. commitment reaches ~$265B per Odaily/Reuters; annual CapEx guidance lifted to $60–64B. 5nm-to-3nm fab conversion timeline accelerated (no specific % capacity figure disclosed publicly).
DRAM's Structural Repricing: Why This Upcycle Is Different — and What It Means for AI Capex
DRAM ASP growth is outpacing unit volume in ways that defy the traditional memory pricing cycle. This analysis examines the supply-side correction mechanics, gross margin expansion dynamics, and capacity investment elasticity reshaping the memory market through 2027.
The current DRAM upcycle is not inventory-led — it is structurally engineered. Suppliers have decoupled revenue growth from bit shipment growth by deliberately restraining conventional capacity additions while redirecting output toward high-margin server and HBM products. If P Equity Research's mid-2027 inflection forecast proves correct, cloud vendors now locking in multi-year contracts may be doing so at or near the cycle peak.
Tower Semiconductor's $3B Japan Photonics Bet: Why METI Is Backing the Mature-Node Play That Advanced Fabs Can't Make
Tower Semiconductor's $3 billion METI-backed silicon photonics and silicon germanium expansion in Japan repositions mature-node capacity at the center of AI data-center infrastructure — and raises pointed questions for procurement teams about photonics supply concentration. Silicon Analysts breaks down the strategic logic, fab economics, and what this means for the broader mature-node supply landscape.
Tower Semiconductor's July 2026 announcement of a $3B dual-track Japan expansion — roughly $1B of which comes from METI grants — is not a conventional capacity story. It is a physics-driven bet that silicon photonics will become a structural bottleneck in AI data-center interconnect, and that the foundry controlling that chokepoint at 300mm scale will command durable pricing power. The updated 2028 revenue target of $3.6B, up from analyst consensus near $2.84B pre-announcement, implies a revenue step-up that, if realized, would fundamentally reprice what a specialty analog foundry is worth in an AI-era supply chain.
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Semiconductor Cost Modeling Platform
Chip Cost Calculator
Model chip manufacturing costs across process nodes from 28nm to 2nm. Calculate GDPW, net die yield, wafer costs, CoWoS packaging, HBM memory pricing, and total chip cost with interactive parameter adjustments. Free alternative to paid die calculators.
Supply Chain Intelligence
Explore 64 semiconductor fabs worldwide with capacity data, track HBM market dynamics with live spot pricing and vendor market share, and visualize supply chain chokepoints from ASML lithography to Japanese photoresist monopolies.
Market Analysis
30+ deep-dive reports covering TSMC wafer pricing, NVIDIA GPU economics, HBM memory shortages, export controls, and AI chip demand trends. Data-driven analysis with interactive cost models and structured data via our free API.
Semiconductor Manufacturing FAQ
- How much does it cost to make a semiconductor chip?
- Semiconductor manufacturing costs vary by process node: mature 28nm costs ~$3,000 per wafer, advanced 5nm costs ~$18,500, and cutting-edge 3nm costs ~$19,500. Per-chip cost depends on die size and yield — for example, an NVIDIA H100 (814mm² at TSMC 4N) costs approximately $3,320 to manufacture, while the B200 costs approximately $6,400.
- How many chips can you get from one wafer?
- The number of chips per wafer (Gross Dies Per Wafer or GDPW) depends on die size and wafer diameter. On a standard 300mm wafer: a small chip (50mm²) yields ~1,250 gross dies, a medium chip (200mm²) yields ~300, and a large chip like NVIDIA's H100 (814mm²) yields approximately 74 gross dies before yield loss.
- What is the most expensive chip to manufacture?
- As of 2026, the most expensive chips to manufacture are large AI accelerators. NVIDIA's B200 (Blackwell) at TSMC 4NP has an estimated manufacturing cost of ~$6,400, with HBM memory ($2,900) being the largest cost component. AMD's MI300X, using N5/N6 chiplets with advanced packaging, costs approximately $5,300 to manufacture.
- How many semiconductor fabs are there in the world?
- Silicon Analysts tracks 64 semiconductor fabrication facilities across 10 countries, operated by 16 companies including TSMC, Samsung, Intel, GlobalFoundries, UMC, and SMIC. New fabs are currently under construction or announced globally, including TSMC Arizona, JASM Kumamoto, and Intel Ohio.
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