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TSMC Commits $100B+ Arizona Expansion, Accelerates 3nm Conversion to Meet AI Chip Surge
TSMC has announced an additional $100 billion investment in its Arizona facilities — part of a broader $265 billion U.S. commitment — and confirmed it is actively converting 5nm capacity to 3nm to meet surging AI chip demand, with CFO Wendell Huang citing a 'strong, multi-year demand mega trend.' Separately, Bloomberg analysis of Moonshot AI's Kimi K3 model highlights that efficiency-optimized AI architectures continue to require large memory footprints, reinforcing sustained structural demand for HBM from suppliers including SK Hynix.
Capacity: TSMC U.S. CapEx raised by +$100B incremental; total U.S. commitment reaches ~$265B per Odaily/Reuters; annual CapEx guidance lifted to $60–64B. 5nm-to-3nm fab conversion timeline accelerated (no specific % capacity figure disclosed publicly).
TSMC $265B US CapEx Commitment + ASML 30% EUV Capacity Surge Signal Multi-Year AI Supply Expansion — with Equipment Price Hike Risk
TSMC has committed an additional $100B in US manufacturing investment (total $265B) while confirming 2026 CapEx at the high end of $52B–$56B guidance, directly supporting CoWoS and advanced-node wafer capacity for AI accelerators including Nvidia H200/B200 SKUs. Concurrently, ASML — the sole supplier of EUV lithography equipment critical to HBM and leading-edge logic fabs — raised its 2026 revenue outlook by ~$6–7B to €43–45B and announced 30% annual production capacity expansion for both EUV and DUV systems over the next two years, while separately reporting active negotiations to raise tool pricing, with TSMC reportedly resisting increases on both EUV and DUV equipment.
TSMC CapEx: +$100B incremental US commitment (total $265B), 2026 CapEx at high end of $52–56B range; ASML EUV/DUV capacity: +30% per year for 2 years; ASML 2026 revenue guidance raised ~15–19% vs prior midpoint (€38B → €44B midpoint); ASML EUV price hike quantum not yet disclosed — wafer/packaging cost pass-through risk flagged but unquantified.
SK Hynix CEO Flags 2027 as Worst-Ever HBM Supply Crunch; $26.5B IPO Capital Earmarked for Capacity Expansion
SK Hynix CEO Kwak Noh-Jung publicly stated that 2027 will represent the worst supply shortage in the memory industry's history, with demand forecast to exceed production capacity beyond 2030, according to a Reuters interview conducted on July 10, 2026. Concurrently, SK Hynix raised $26.5B in its Nasdaq ADR debut — the largest-ever US IPO by a foreign company — with proceeds explicitly allocated to a new South Korean fab, a new packaging facility, and EUV scanner procurement to address AI-driven HBM demand.
Capacity expansion funded: $26.5B raised (new fab + packaging facility + EUV scanners); Supply gap: demand forecasted to exceed supply through 2030+; No specific yield or price-per-unit figure disclosed.
China's AI Chip Bifurcation: How Export Controls Are Accelerating a Parallel Semiconductor Ecosystem
US export controls have not slowed China's semiconductor ambitions — they have restructured them. This analysis examines the localization trajectory, the hard bottlenecks that remain, and what a bifurcated AI chip ecosystem means for global supply chains by 2030.
China's semiconductor localization drive has shifted from a long-term ambition to an urgent industrial mobilization, with SMIC capex, domestic equipment share, and AI chip design activity all accelerating in response to successive rounds of US export controls. The ecosystem is making measurable progress at mature and mid-range nodes while confronting structural limits in EUV lithography and advanced memory — limits that define the ceiling of near-term self-reliance. The result is not one global AI chip market but two diverging ones, with compounding cost, performance, and supply-chain consequences for every corporate buyer and strategic planner operating across both.
Export Controls, Capex Reallocation, and the Rewiring of the Allied Supply Chain
US export controls on advanced semiconductors are forcing a structural reallocation of capex across the allied supply chain, reshaping where fabs get built, how memory is sourced, and how procurement teams manage escalating geopolitical risk. This analysis breaks down the mechanics and strategic implications.
US export controls have moved well beyond a China-containment instrument — they are now a primary driver of capex geography, domestic sourcing mandates, and supply-chain architecture decisions across the entire semiconductor industry. Allied governments and leading chipmakers are responding with investment realignments that carry lasting cost and risk implications for every link in the chain.
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Semiconductor Cost Modeling Platform
Chip Cost Calculator
Model chip manufacturing costs across process nodes from 28nm to 2nm. Calculate GDPW, net die yield, wafer costs, CoWoS packaging, HBM memory pricing, and total chip cost with interactive parameter adjustments. Free alternative to paid die calculators.
Supply Chain Intelligence
Explore 64 semiconductor fabs worldwide with capacity data, track HBM market dynamics with live spot pricing and vendor market share, and visualize supply chain chokepoints from ASML lithography to Japanese photoresist monopolies.
Market Analysis
30+ deep-dive reports covering TSMC wafer pricing, NVIDIA GPU economics, HBM memory shortages, export controls, and AI chip demand trends. Data-driven analysis with interactive cost models and structured data via our free API.
Semiconductor Manufacturing FAQ
- How much does it cost to make a semiconductor chip?
- Semiconductor manufacturing costs vary by process node: mature 28nm costs ~$3,000 per wafer, advanced 5nm costs ~$18,500, and cutting-edge 3nm costs ~$19,500. Per-chip cost depends on die size and yield — for example, an NVIDIA H100 (814mm² at TSMC 4N) costs approximately $3,320 to manufacture, while the B200 costs approximately $6,400.
- How many chips can you get from one wafer?
- The number of chips per wafer (Gross Dies Per Wafer or GDPW) depends on die size and wafer diameter. On a standard 300mm wafer: a small chip (50mm²) yields ~1,250 gross dies, a medium chip (200mm²) yields ~300, and a large chip like NVIDIA's H100 (814mm²) yields approximately 74 gross dies before yield loss.
- What is the most expensive chip to manufacture?
- As of 2026, the most expensive chips to manufacture are large AI accelerators. NVIDIA's B200 (Blackwell) at TSMC 4NP has an estimated manufacturing cost of ~$6,400, with HBM memory ($2,900) being the largest cost component. AMD's MI300X, using N5/N6 chiplets with advanced packaging, costs approximately $5,300 to manufacture.
- How many semiconductor fabs are there in the world?
- Silicon Analysts tracks 64 semiconductor fabrication facilities across 10 countries, operated by 16 companies including TSMC, Samsung, Intel, GlobalFoundries, UMC, and SMIC. New fabs are currently under construction or announced globally, including TSMC Arizona, JASM Kumamoto, and Intel Ohio.
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