Silicon Analysts

How much does your chip cost to manufacture?

Free interactive tools for semiconductor cost modeling, fab tracking, and supply chain analysis. Trusted by 1,000+ engineers monthly and cited by ChatGPT, Perplexity, and Gemini.

1,000+ monthly usersCited by ChatGPT & Perplexity64 fabs · 13 AI chips · 30+ reports

Analysis & Modeling Tools

From wafer-level cost modeling to global supply chain mapping — everything in one platform.

Cost Modeling

Chip Price Calculator

Wafer cost, yield modeling, packaging economics, and margin analysis across process nodes from 180nm to 2nm.

180nm–2nm · 8 foundriesApril 2026
Cost Modeling

Packaging Model

Compare CoWoS-S, CoWoS-L, EMIB, SoIC, and flip-chip architectures with HBM stack cost analysis.

5 architectures · HBM stacksApril 2026
Supply Chain

Fab Explorer

Explore 64 semiconductor fabs from TSMC, Samsung, Intel, GlobalFoundries, SMIC, UMC, and more. Filter by node, country, and capacity.

64 fabs · 10 countriesApril 2026
Benchmarking

Price / Performance Frontier

Compare AI accelerators on cost, throughput, training time, and TCO — H100, B200, MI300X, TPU v5p, and more.

12 accelerators · 4 metricsApril 2026
Market IntelligenceNEW

HBM Market Analysis

HBM market dynamics — accelerator specs, vendor market share, spot pricing, supply chain signals, and revenue forecasts.

14 datasets · Live dataLive data
Cost ModelingUPDATED

Cost Bridge Chart

Side-by-side manufacturing cost comparison across logic die, HBM memory, packaging, and assembly for 13 AI accelerators.

13 chips · 4 cost layersApril 2026
Market IntelligenceNEW

Market Data

Historical time series for wafer pricing, HBM/DRAM costs, fab utilization, CoWoS capacity, and NRE trends — 225 sourced data points across 14 datasets.

14 datasets · 225 data pointsMar 2026
Supply ChainNEW

Supply Chain Explorer

Interactive sunburst visualization of semiconductor supply chain chokepoints — from ASML to Zeiss optics to Japanese photoresist monopolies.

12 chokepoints · 7 countriesApril 2026
Supply ChainNEW

Allocation Dashboard

Track foundry allocation status, CoWoS packaging availability, and HBM supply signals across 14 process nodes from TSMC, Samsung, Intel, and more.

14 nodes · 3 packaging · 3 HBMApril 2026
Decision ToolsNEW

Tapeout Decision Workspace

Guided 5-step workflow for fabless teams evaluating tapeout decisions — chip definition, foundry selection, cost modeling, competitive benchmarking, and go/no-go summary.

5 steps · 40+ benchmarksApril 2026
$ curl /api/v1/accelerators
{ "success": true, "data": [...] }
$ curl /api/v1/articles?q=nvidia
{ "count": 11 }
$ curl /api/v1/hbm
APINEW

Developer API

Structured semiconductor data for AI agents and applications — accelerator costs, HBM market data, and 30+ articles. Free, no key required.

4 endpoints · JSONApril 2026

Featured Analysis

NVIDIA B200 Manufacturing Cost: $6,400 per chip — 84% gross margin at $40k sell price

See full cost breakdown →

Latest Analysis

Deep-dive reports on semiconductor technology, supply chains, and market dynamics

ANALYSIS

Why CoWoS Lead Times — Not Wafer Capacity — Are the Real AI Bottleneck

TSMC is nearly doubling CoWoS capacity in 2026, yet lines stay booked at 52–78 week lead times. Why the booking window, not raw capacity, is the binding constraint on AI hardware.

The standard read on AI hardware supply — 'TSMC is adding CoWoS capacity, so the shortage will ease' — uses the wrong metric. Monthly capacity is rising fast (an estimated ~75–80k toward a 120–130k WPM target by end-2026), but it is being pre-booked faster than it comes online: an estimated 85%+ of 2026–2027 capacity is already locked, and NVIDIA alone reportedly booked more than half of the expansion. The result is that lead times stay at 52–78 weeks even as capacity nearly doubles. The metric that actually gates AI accelerator supply is the booking window — lead time over time — not instantaneous WPM, and almost no one publishes it as tracked data.

FOUNDRY

Foundry Allocation Status 2026: Where Capacity Is and Isn't

Mid-2026 foundry allocation map: TSMC CoWoS fully booked with ~1M wafers of 2026 demand, NVIDIA ~60% locked, 2nm booked through 2028, HBM allocated. Live tracker + API.

Advanced-packaging allocation, not wafer starts, is the binding constraint on AI hardware in 2026. TSMC's CoWoS lines — both CoWoS-S and CoWoS-L — are fully booked, against total 2026 demand estimated near 1.0 million wafers (up from ~370k in 2024). NVIDIA alone is estimated to hold roughly 60% (~595k wafers) and has reportedly booked more than half of TSMC's 2026–2027 CoWoS expansion; the top three customers together account for an estimated >85% of capacity. Leading-edge 2nm is booked well into 2028 and HBM is allocated through 2026. These are sourced public estimates — most trace to a single sell-side house reproduced across outlets — so every datapoint in our live tracker carries a source, date, and confidence tier.

MEMORY

The HBM Qualification Race: Who Actually Passed Whose Qual, 2022–2026

A sourced, dated reconstruction of every major HBM qualification milestone from SK Hynix's industry-first HBM3 for the NVIDIA H100 in 2022 through all three vendors entering HBM4 volume production for Vera Rubin in 2026 — including Samsung's three failed attempts at NVIDIA's 12-Hi HBM3E qual and what qualification timing did to market share.

HBM market share is not decided by fab capacity or roadmap announcements — it is decided at qualification. Samsung's ~18-month struggle to pass NVIDIA's 12-Hi HBM3E validation (April 2024 to September 2025) cost it the Blackwell cycle while Micron, a late entrant, converted early qualification into real share. HBM4 marks the first generation where all three vendors qualified at the start of the ramp, which shifts the competitive question from "who can ship?" to "who can ship at yield and price?"

AI HARDWARE

What Does an NVIDIA B200 Cost to Make? Now Claude Can Tell You.

The first semiconductor cost data MCP server on the Anthropic registry. Add Silicon Analysts to Claude in 30 seconds and ask real questions about chip economics.

Until now, asking Claude about chip manufacturing costs returned training-data approximations — best-effort guesses that drifted further from reality every month. Silicon Analysts MCP changes that: Claude now reaches into a live database of accelerator BOMs, HBM pricing, wafer costs, and packaging benchmarks while it's talking to you. The setup takes 30 seconds. The semiconductor industry just got its first AI-native data layer.

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Silicon Analysts Pro

Custom cost models, data exports, price alerts, and exclusive analysis for semiconductor professionals.

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Why Silicon Analysts

Industry-Standard Models

Built on semiconductor cost models used by leading companies. Wafer pricing, yield curves, and packaging economics from publicly available data.

Real-Time Market Data

Live ticker, HBM spot prices, and fab capacity tracking. Stay ahead of supply chain shifts with structured, programmatic data access.

Open & Transparent

Free tools, public API, documented data sources. No black boxes — every estimate links to methodology and cited research.

Semiconductor Cost Modeling Platform

Chip Cost Calculator

Model chip manufacturing costs across process nodes from 28nm to 2nm. Calculate GDPW, net die yield, wafer costs, CoWoS packaging, HBM memory pricing, and total chip cost with interactive parameter adjustments. Free alternative to paid die calculators.

Supply Chain Intelligence

Explore 64 semiconductor fabs worldwide with capacity data, track HBM market dynamics with live spot pricing and vendor market share, and visualize supply chain chokepoints from ASML lithography to Japanese photoresist monopolies.

Market Analysis

30+ deep-dive reports covering TSMC wafer pricing, NVIDIA GPU economics, HBM memory shortages, export controls, and AI chip demand trends. Data-driven analysis with interactive cost models and structured data via our free API.

Semiconductor Manufacturing FAQ

How much does it cost to make a semiconductor chip?
Semiconductor manufacturing costs vary by process node: mature 28nm costs ~$3,000 per wafer, advanced 5nm costs ~$18,500, and cutting-edge 3nm costs ~$19,500. Per-chip cost depends on die size and yield — for example, an NVIDIA H100 (814mm² at TSMC 4N) costs approximately $3,320 to manufacture, while the B200 costs approximately $6,400.
How many chips can you get from one wafer?
The number of chips per wafer (Gross Dies Per Wafer or GDPW) depends on die size and wafer diameter. On a standard 300mm wafer: a small chip (50mm²) yields ~1,250 gross dies, a medium chip (200mm²) yields ~300, and a large chip like NVIDIA's H100 (814mm²) yields approximately 74 gross dies before yield loss.
What is the most expensive chip to manufacture?
As of 2026, the most expensive chips to manufacture are large AI accelerators. NVIDIA's B200 (Blackwell) at TSMC 4NP has an estimated manufacturing cost of ~$6,400, with HBM memory ($2,900) being the largest cost component. AMD's MI300X, using N5/N6 chiplets with advanced packaging, costs approximately $5,300 to manufacture.
How many semiconductor fabs are there in the world?
Silicon Analysts tracks 64 semiconductor fabrication facilities across 10 countries, operated by 16 companies including TSMC, Samsung, Intel, GlobalFoundries, UMC, and SMIC. New fabs are currently under construction or announced globally, including TSMC Arizona, JASM Kumamoto, and Intel Ohio.

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