The live ledger of AI-chip economics
A provenance-backed data platform for semiconductor & AI-accelerator economics — wafer pricing, HBM, packaging, fabs, and foundry allocation. Every number dated and sourced, every dataset queryable by humans and AI agents alike.
TSMC wafer price by node
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Chip Price Calculator
Wafer cost, yield modeling, packaging economics, and margin analysis across process nodes from 180nm to 2nm.
HBM Market Analysis
HBM market dynamics — accelerator specs, vendor market share, spot pricing, supply chain signals, and revenue forecasts.
Fab Explorer
Explore 64 semiconductor fabs from TSMC, Samsung, Intel, GlobalFoundries, SMIC, UMC, and more. Filter by node, country, and capacity.
Market Data
Historical time series for wafer pricing, HBM/DRAM costs, fab utilization, CoWoS capacity, and NRE trends — 328 sourced data points across 16 datasets.
Cost Bridge Chart
Side-by-side manufacturing cost comparison across logic die, HBM memory, packaging, and assembly for 18 AI accelerators.
Packaging Model
Compare CoWoS-S, CoWoS-L, EMIB, SoIC, and flip-chip architectures with HBM stack cost analysis.
Supply Chain Explorer
Interactive sunburst visualization of semiconductor supply chain chokepoints — from ASML to Zeiss optics to Japanese photoresist monopolies.
Price / Performance Frontier
Compare AI accelerators on cost, throughput, training time, and TCO — H100, B200, MI300X, TPU v5p, and more.
Allocation Dashboard
Track foundry allocation status, CoWoS packaging availability, and HBM supply signals across 14 process nodes from TSMC, Samsung, Intel, and more.
Tapeout Decision Workspace
Guided 5-step workflow for fabless teams evaluating tapeout decisions — chip definition, foundry selection, cost modeling, competitive benchmarking, and go/no-go summary.
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Structured semiconductor data for AI agents and applications — wafer pricing, HBM, foundry economics, the daily change ledger, and 30+ articles. Free, no key required.
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Latest Analysis & Market Intelligence
Deep-dive reports and daily AI-detected supply-chain signals — each sourced and dated. Public sources only.
SK Hynix Breaks Ground on Indiana HBM Fab: $4B US Domestic Capacity Confirmed
SK Hynix formally broke ground on its Indiana HBM production facility on August 27–28, 2026, committing approximately $4B in US-based HBM manufacturing capacity with volume production targeted from 2029 onward. This represents the first confirmed US-soil HBM fab groundbreaking by a major memory supplier, establishing a new domestic supply node for AI accelerator customers such as Nvidia.
CapEx commitment: ~$4B USD; production ramp targeted 2029; near-term (2026–2028) HBM supply capacity unchanged.
SK Hynix Breaks Ground on $4B+ Indiana HBM4E Packaging Facility; HBM Shortage Forecast Through 2030
SK Hynix formally broke ground on its first U.S. advanced HBM packaging facility in West Lafayette, Indiana on August 27, 2026, committing more than $4 billion toward a cleanroom targeted for completion by October 2028 and HBM4E mass production in Q3 2029. SK Hynix CEO Kwak Noh-Jung simultaneously stated the company expects the current memory chip shortage to persist through the end of 2030, signaling a multi-year structural supply deficit for HBM used in AI accelerators including Nvidia H200 and B-series products.
Capacity: +U.S. HBM4E packaging base online Q3 2029 (net-new domestic capacity); CapEx committed: >$4B; Supply gap: HBM shortage characterized as persisting through end-2030 per SK Hynix CEO public statement.
Nvidia Flags 'Extreme' Memory Costs Compressing Margins; Supply Meets Only 70% of Demand — HBM Shortage Structural, Not Transient
Nvidia's Q2 FY2027 earnings (revenue $96.2B, +106% YoY) included an explicit management warning that memory costs are 'extreme' and surpassed internal forecasts, forcing a gross margin guidance reset for the coming year; Nvidia simultaneously disclosed it can currently supply only 70% of demand from existing customers. A former Nvidia executive cited on CNBC corroborated the view that elevated memory pricing is structural, arguing Nvidia's own 70% FY2028 revenue growth projection — explicitly characterized by CFO Colette Kress as a 'supply-constrained outlook' — would be higher were HBM constraints not binding.
Gross margin pressure: Nvidia guiding below current ~75% GM due to memory cost overage; supply gap: ~30% of current customer demand unmet; FY2028 revenue upside capped by HBM supply constraint (analyst Stacy Rasgon, Bernstein, quantifies constrained vs. unconstrained delta as implying >$200B in suppressed revenue potential).
The $5,000 Graphics Card: How AI Demand and GDDR7 Scarcity Are Restructuring the Discrete GPU Market
RTX 5090 pricing has surged to more than $5,000 — 2.5x its $1,999 MSRP — as AI-driven GDDR7 memory competition and structural supply constraints reshape discrete GPU market economics for corporate procurement teams and strategic planners.
The discrete GPU market is experiencing a supply-demand dislocation that is categorically different from the 2020–2022 shortage cycle: the binding constraint has shifted from logic die fabrication capacity to GDDR7 memory allocation, and AI inference workloads running on consumer-class hardware are now a measurable demand input alongside gaming. With NVIDIA holding roughly 90% of discrete GPU add-in-board shipments and the RTX 5090 trading at more than 2.5x its launch MSRP, corporate procurement teams face a market where the traditional MSRP anchor has become largely notional for flagship SKUs.
Which Node Runs at TSMC Fab 12, 14 and 15? Four Public Answers, One Filing
Ask which process node runs at TSMC's Fab 12, Fab 14 and Fab 15 and the public record gives you four different answers, none of them TSMC's. TSMC files the answer every year in its Form 20-F, fab by fab, and has for eight filings. We read the column, found our own registry was the furthest off, corrected 29 rows, and here explain what the filing says, what it does to node-level capacity totals, and what it cannot settle.
The most-cited public trackers do not agree with each other on which node three of TSMC's largest fabs run, and none of them agree with the one document that is legally required to say: TSMC's annual Form 20-F. Our own fab registry was the furthest from the filing, booking Fab 15 to 3 nm while TSMC has listed it at 7 nm in every filing since 2018. Following the filing makes our 3 nm roll-up reconcile to TSMC's stated target exactly, moves 7 nm from a 48% overshoot to a 24% shortfall, and reveals that 80 kWSPM of "5 nm" capacity was parked at fabs where TSMC says no 5 nm runs in volume. The numbers that everyone repeats are not wrong because they are old. They are wrong because nobody reads the table.
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Semiconductor Cost Modeling Platform
Chip Cost Calculator
Model chip manufacturing costs across process nodes from 28nm to 2nm. Calculate GDPW, net die yield, wafer costs, CoWoS packaging, HBM memory pricing, and total chip cost with interactive parameter adjustments. Free alternative to paid die calculators.
Supply Chain Intelligence
Explore 64 semiconductor fabs worldwide with capacity data, track HBM market dynamics with live spot pricing and vendor market share, and visualize supply chain chokepoints from ASML lithography to Japanese photoresist monopolies.
Market Analysis
30+ deep-dive reports covering TSMC wafer pricing, NVIDIA GPU economics, HBM memory shortages, export controls, and AI chip demand trends. Data-driven analysis with interactive cost models and structured data via our free API.
Semiconductor Manufacturing FAQ
- How much does it cost to make a semiconductor chip?
- Semiconductor manufacturing costs vary by process node: mature 28nm costs ~$3,000 per wafer, advanced 5nm costs ~$18,500, and cutting-edge 3nm costs ~$19,500. Per-chip cost depends on die size and yield — for example, an NVIDIA H100 (814mm² at TSMC 4N) costs approximately $3,320 to manufacture, while the B200 costs approximately $6,400.
- How many chips can you get from one wafer?
- The number of chips per wafer (Gross Dies Per Wafer or GDPW) depends on die size and wafer diameter. On a standard 300mm wafer: a small chip (50mm²) yields ~1,250 gross dies, a medium chip (200mm²) yields ~300, and a large chip like NVIDIA's H100 (814mm²) yields approximately 74 gross dies before yield loss.
- What is the most expensive chip to manufacture?
- As of 2026, the most expensive chips to manufacture are large AI accelerators. NVIDIA's B200 (Blackwell) at TSMC 4NP has an estimated manufacturing cost of ~$6,750, with HBM memory ($3,250) being the largest cost component. AMD's MI300X, using N5/N6 chiplets with advanced packaging, costs approximately $5,300 to manufacture.
- How many semiconductor fabs are there in the world?
- Silicon Analysts tracks 64 semiconductor fabrication facilities across 10 countries, operated by 16 companies including TSMC, Samsung, Intel, GlobalFoundries, UMC, and SMIC. New fabs are currently under construction or announced globally, including TSMC Arizona, JASM Kumamoto, and Intel Ohio.
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