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Eight AI hardware bottlenecks — CoWoS, HBM, ABF substrates, T-glass, InP lasers — judged weekly from company filings, with graded evidence and customer deposits. The supply-chain chokepoint map sits below it.
Cost Bridge Chart
Side-by-side manufacturing cost comparison across logic die, HBM memory, packaging, and assembly for 18 AI accelerators.
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Track foundry allocation status, CoWoS packaging availability, and HBM supply signals across 14 process nodes from TSMC, Samsung, Intel, and more.
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GPU rental $/hr across CoreWeave, Lambda, AWS, and spot markets, tracked daily — plus discount tiers and price-change history for H100, H200, and B200.
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Total cost of ownership for an AI training cluster — GPUs, networking, power, cooling, and staffing across cluster sizes and deployment models, with an equivalent-cloud cost comparison.
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Nvidia Locks In Packaging Capacity: Amkor Interposer 4x, Substrates 2.5x, $1.1B KYEC Prepay
Nvidia has signed a set of capacity expansion agreements across its advanced packaging and test supply chain, targeting a more than fourfold increase in Amkor interposer wafer capacity by end-2028 (combined Arizona and South Korea commitments now $3B), a 2.5x increase in package substrate capacity over three years, a 15x expansion of SPIL optical-engine capacity by mid-2027, and $1.1B of capacity reservation financing to KYEC for U.S. test facilities. The deals also cover Samsung Electro-Mechanics ABF substrate output in Korea and IBIDEN substrate capacity in Japan, signaling that interposer, substrate and test — not GPU die — are the binding constraints on AI accelerator output.
Interposer wafer capacity: >+300% by end-2028 (Amkor); package substrate capacity: +150% (2.5x) over three years; optical-engine capacity: 15x by mid-2027 then 2x more by end-2028 (SPIL); Nvidia commitments: $3B Amkor (AZ + S. Korea), $1.1B KYEC advance
NVIDIA Locks In 2.5x Substrate and 4x Interposer Capacity With Six Suppliers
NVIDIA announced at GTC Berlin on October 21, 2026 a multi-process capacity expansion with six suppliers — Ibiden, Samsung Electro-Mechanics and Unimicron (package substrates), Amkor (interposer wafers), KYEC (test) and SPIL (CPO optical engines) — targeting a 2.5x increase in NVIDIA-dedicated substrate capacity over three years. Amkor's Korean interposer wafer capacity is targeted to rise more than 300% by end-2028, SPIL's optical engine output 15x by mid-2027 with a further doubling by end-2028, and NVIDIA's overall test capacity to double between 2026 and 2027, with Jensen Huang stating 'Demand is extraordinary. Capacity is the constraint.'
Package substrate capacity: +150% (2.5x) over three years; interposer wafer capacity: +300%+ by end-2028; CPO optical engine capacity: 15x by mid-2027, 2x again by end-2028; test capacity: 2x from 2026 to 2027; Samsung Electro-Mechanics FC-BGA supply to NVIDIA growing at double-digit annual rates from 2026
Samsung to Use TSMC 3nm for Base Dies of Nvidia Custom HBM
Reuters, citing a Seoul newspaper, reported on October 18, 2026 that Samsung Electronics will use TSMC's 3-nanometre process to fabricate the base (logic) dies for Nvidia's next-generation custom high-bandwidth memory, an unusual foundry-memory crossover that places a key HBM component on TSMC logic capacity. Separately, TSMC confirmed on its Q3 2026 earnings call that it will add another 3nm fab in Tainan with production in 1H 2028, held 2026 CapEx at $60–64B, and said demand still far exceeds supply capacity, while its second Arizona fab completed construction with mass production pulled ahead to Q3 2027.
N/A (no unit pricing disclosed); TSMC 2026 CapEx maintained at $60–64B, new Tainan 3nm fab production 1H 2028, Arizona Fab 2 mass production Q3 2027
The Long March Through Lithography: China's Equipment Push, Capex Reallocation, and the Limits of Localization
China's semiconductor equipment localization is accelerating across etch, deposition, and cleaning segments, but the EUV gap and process integration challenges mean the timeline to advanced-node self-sufficiency remains measured in decades, not years.
China is executing a disciplined, segment-by-segment equipment localization strategy that is already reshaping mature-node fab economics and redirecting capex away from ASML-dependent advanced nodes. The domestic AI accelerator market is on track for roughly 50% localization by share in 2026 per TrendForce, but the photolithography gap — particularly at EUV — remains the structural ceiling on how far that momentum can reach into sub-7nm production. Procurement teams and strategic planners should treat the next three to five years as a period of accelerating bifurcation, not imminent convergence.
The Framework Is the Policy: How the US Export Control Architecture for AI Chips Is Being Rebuilt in Real Time
The 2026 US export control framework for AI chips is no longer a single rule — it is a layered, evolving architecture of node-based thresholds, per-chip licensing conditions, and geopolitical leverage points. This analysis examines what changed, why it matters, and how China is responding.
The H200 saga of early 2026 — banned, unbanned, then re-conditioned within weeks — reveals that US export control policy is no longer a stable regulatory environment but an active, frequently revised instrument of strategic competition. The shift from presumption of denial to case-by-case review does not signal liberalization; it signals a more granular targeting regime. China's response, a combination of domestic chip mandates, capital redirection, and selective import conditioning, suggests that the bifurcation of the global AI semiconductor ecosystem is now structural, not cyclical.
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Semiconductor Cost Modeling Platform
Chip Cost Calculator
Model chip manufacturing costs across process nodes from 28nm to 2nm. Calculate GDPW, net die yield, wafer costs, CoWoS packaging, HBM memory pricing, and total chip cost with interactive parameter adjustments. Free alternative to paid die calculators.
Supply Chain Intelligence
Explore 64 semiconductor fabs worldwide with capacity data, track HBM market dynamics with qualification status and vendor market share, and visualize supply chain chokepoints from ASML lithography to Japanese photoresist monopolies.
Market Analysis
88 deep-dive reports covering TSMC wafer pricing, NVIDIA GPU economics, HBM memory shortages, export controls, and AI chip demand trends. Data-driven analysis with interactive cost models and structured data via our free API.
Semiconductor Manufacturing FAQ
- How much does it cost to make a semiconductor chip?
- Semiconductor manufacturing costs vary by process node: mature 28nm costs ~$3,000 per wafer, advanced 5nm costs ~$18,500, and cutting-edge 3nm costs ~$19,500. Per-chip cost depends on die size and yield — for example, an NVIDIA H100 (814mm² at TSMC 4N) costs approximately $3,320 to manufacture, while the B200 costs approximately $6,400.
- How many chips can you get from one wafer?
- The number of chips per wafer (Gross Dies Per Wafer or GDPW) depends on die size and wafer diameter. On a standard 300mm wafer: a small chip (50mm²) yields ~1,250 gross dies, a medium chip (200mm²) yields ~300, and a large chip like NVIDIA's H100 (814mm²) yields approximately 74 gross dies before yield loss.
- What is the most expensive chip to manufacture?
- As of 2026, the most expensive chips to manufacture are large AI accelerators. NVIDIA's B200 (Blackwell) at TSMC 4NP has an estimated manufacturing cost of ~$6,750, with HBM memory ($3,250) being the largest cost component. AMD's MI300X, using N5/N6 chiplets with advanced packaging, costs approximately $5,300 to manufacture.
- How many semiconductor fabs are there in the world?
- Silicon Analysts tracks 64 semiconductor fabrication facilities across 10 countries, operated by 16 companies including TSMC, Samsung, Intel, GlobalFoundries, UMC, and SMIC. New fabs are currently under construction or announced globally, including TSMC Arizona, JASM Kumamoto, and Intel Ohio.
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