How much does a TSMC wafer cost in 2026?

TSMC wafer costs in 2026: 3nm (N3/N3E) averages ~$19,500 per wafer (range $17,000–$22,000). 5nm (N5) averages ~$18,500 ($16,000–$21,300). 7nm (N7) averages ~$9,500 ($8,100–$10,900). 28nm averages ~$3,000 ($2,550–$3,450). Samsung 3nm is approximately 20–25% cheaper at ~$15,000 per wafer.

How much does HBM memory cost?

HBM3 costs approximately $200 per 24GB stack. HBM3E costs approximately $300 per 36GB stack. HBM2e costs approximately $120 per 16GB stack. HBM4 (next generation) is expected to cost approximately $500 per 48GB stack. HBM commands a 5–6× premium over equivalent DDR5 capacity due to 3D stacking complexity.

How much does CoWoS packaging cost?

TSMC CoWoS-S 2.5D packaging costs approximately $70 per unit for standard interposer configurations. CoWoS-L (for larger multi-die designs) costs approximately 20–40% more. Intel EMIB costs approximately $35 per unit. 3D stacking (SoIC) costs approximately $120 per unit. CoWoS lead times are 40–52 weeks as of early 2026.

What is the cost breakdown of an NVIDIA H100?

The NVIDIA H100 SXM5 has an estimated manufacturing cost of ~$3,320: logic die cost ~$300 (814mm² on TSMC 4N), HBM3 memory ~$1,350 (six stacks, 80GB), CoWoS-S packaging ~$750, plus test and assembly. NVIDIA sells the H100 at approximately $28,000, yielding a gross margin of approximately 88%.

Why are chip manufacturing costs increasing?

Three main factors: (1) EUV lithography — advanced nodes require multi-pass EUV patterning, dramatically increasing wafer cost. TSMC 3nm wafers cost roughly 6.5× more than 28nm. (2) Advanced packaging — CoWoS, HBM integration, and multi-die architectures add $500–$1,500+ per chip. (3) Memory bandwidth — AI workloads require 6–8 HBM stacks costing $1,200–$2,400 per chip. These three costs didn't exist or were negligible at older nodes.

How much does it cost to design a chip?

Chip design costs (NRE) have escalated dramatically. A 28nm chip design costs approximately $30–50M. A 7nm design costs $100–200M. A 5nm design costs $200–400M. A 3nm design costs $400–600M+. These costs include EDA tools, IP licensing, mask sets ($10–20M at 3nm), engineering headcount, and verification/validation.

What determines chip manufacturing yield?

Yield depends on die size, defect density (D0), and process maturity. TSMC 3nm has a D0 of ~0.09–0.14 defects/cm² (early vs mature production). Larger dies have exponentially lower yields — an 814mm² H100 die yields roughly 40–50%, while a 100mm² chip yields 85–95%. Yield directly determines cost per die since lower yield means fewer good chips per wafer.

How Much Does It Cost to Make a Semiconductor Chip?

A complete guide to semiconductor chip manufacturing costs in 2026. Covers wafer pricing by process node, HBM memory economics, advanced packaging costs, and full cost breakdowns for leading AI accelerators.

Last updated: February 2026 · Data sources: Industry estimates, TSMC/Samsung public filings, teardown analysis · Model your own chip costs →

Quick answer: Semiconductor chip manufacturing costs range from $1–5 for a simple IoT chip (28nm) to $3,000–13,000+ for a cutting-edge AI accelerator (3nm with HBM and CoWoS packaging). The three biggest cost drivers are the wafer ($3,000–$20,000 per wafer depending on node), HBM memory ($200–$300 per stack × 6–8 stacks), and advanced packaging ($70–$120 per unit).

Wafer Costs by Process Node

Wafer cost is the foundation of chip economics. Prices vary by foundry, node, volume, and contract terms. Leading-edge nodes (3nm, 5nm) use EUV lithography, which drives costs significantly higher than mature nodes.

Node	Foundry	Avg Wafer Cost	Range
3nm	TSMC N3/N3E	$19,500	$17,000–$22,000
3nm	Samsung 3GAE	$15,000	$13,000–$17,000
5nm	TSMC N5/N4	$18,500	$16,000–$21,300
5nm	Samsung 5nm	$13,000	$11,000–$15,000
7nm	TSMC N7	$9,500	$8,100–$10,900
16nm	Intel	$4,500	$3,800–$5,200
28nm	TSMC	$3,000	$2,550–$3,450

Source: TrendForce, Morgan Stanley, CSET, industry consensus estimates. Model specific wafer costs →

Packaging Costs

Advanced packaging has become a major cost component and supply bottleneck. AI accelerators require 2.5D or 3D packaging to integrate HBM memory stacks alongside logic dies.

Package Type	Cost per Unit	Typical Use
QFN	$0.80	Cost-optimized IoT/MCU
FC-BGA (flip-chip)	$8	Standard CPUs, GPUs
FOWLP/InFO	$15	Mobile SoCs (Apple A-series)
Intel EMIB	$35	2.5D bridge (Ponte Vecchio)
TSMC CoWoS	$70	2.5D interposer (H100, MI300X)
TSMC SoIC (3D)	$120	3D stacking (AMD chiplets)

CoWoS demand exceeds supply by 40–50% with lead times of 40–52 weeks. Model packaging costs →

Memory Costs (HBM, DRAM)

High Bandwidth Memory (HBM) is the fastest-growing cost component for AI chips. Each stack uses through-silicon vias (TSVs) to vertically connect multiple DRAM dies, delivering 5–10× the bandwidth of standard GDDR.

Memory Type	Cost / Stack	Capacity / Stack	Bandwidth / Stack
HBM2e	$120	16 GB	460 GB/s
HBM3	$200	24 GB	819 GB/s
HBM3E	$300	36 GB	1.18 TB/s
HBM4 (est.)	$500	48 GB	>2 TB/s

SK Hynix leads with ~50–55% market share, followed by Samsung (~35–40%) and Micron (~5–10%). Full HBM market analysis →

AI Chip Cost Breakdowns

Estimated manufacturing cost breakdowns for major AI accelerators. All costs are bill-of-materials (BOM) estimates excluding design (NRE) costs.

NVIDIA H100 SXM5

Component	Est. Cost	Details
Logic Die	$300	814mm², TSMC 4N
HBM3 Memory	$1,350	6 stacks × $200, 80GB total
CoWoS-S Packaging	$750	2.5D silicon interposer
Test & Assembly	~$920	Substrate, test, assembly
Total Manufacturing	~$3,320	Sell price: ~$28,000 (88% margin)

NVIDIA B200

Component	Est. Cost	Details
Logic Dies (2×)	~$600	2× ~800mm², TSMC 4NP (Blackwell)
HBM3E Memory	~$2,400	8 stacks × $300, 192GB total
CoWoS-L Packaging	~$1,000	Organic interposer + LSI bridges
Test & Assembly	~$2,400	Multi-die module complexity
Total Manufacturing	~$6,400	Sell price: ~$40,000 (84% margin)

AMD MI300X

Component	Est. Cost	Details
Logic Chiplets	~$1,500	Multi-die, TSMC N5/N6, 1,725mm² total
HBM3 Memory	~$1,600	8 stacks × $200, 192GB total
SoIC/3D Packaging	~$1,200	3D stacking + CoWoS integration
Test & Assembly	~$1,000	Complex multi-die module
Total Manufacturing	~$5,300	Sell price: ~$15,000 (65% margin)

Source: Epoch AI, Raymond James, TrendForce, SemiAnalysis teardown data. Compare any two chips side by side →

Why Chip Manufacturing Costs Are Rising

Moore's Law historically delivered both more transistors and lower cost per transistor. That economic equation broke at the 5nm node. Three structural shifts are driving costs higher:

EUV lithography costs: Advanced nodes require multi-pass EUV patterning. TSMC 3nm wafers cost ~6.5× more than 28nm. Each EUV scanner costs $350M+.
Advanced packaging overhead: CoWoS, SoIC, and HBM integration add $500–$1,500+ per chip — cost layers that didn't exist at older nodes.
Memory bandwidth demands: AI workloads require 6–8 HBM stacks per chip at $200–$300 each, adding $1,200–$2,400 to BOM. This is the fastest-growing cost component.

The result: while a 28nm chip's BOM might be $3–10, a leading-edge AI chip's BOM is $3,000–$13,000 — a 1,000× increase driven by packaging and memory, not just the silicon.

Interactive Cost Modeling

Use our free tools to model specific chip cost scenarios:

Methodology & Data Sources

Cost estimates on this page are derived from multiple sources:

Epoch AI Monte Carlo cost models
Raymond James semiconductor equity research
TrendForce quarterly foundry reports
SemiAnalysis teardown and cost analysis
Official vendor spec sheets (NVIDIA, AMD, Intel)
CSET (Georgetown) semiconductor cost research

Data last updated: February 8, 2026. All costs are estimates and may vary by volume, contract terms, and market conditions. This data is available programmatically via our free JSON API.

Frequently Asked Questions

How much does it cost to make a semiconductor chip?: Semiconductor chip manufacturing cost varies enormously. A simple IoT chip on 28nm costs $1–5 per die. A mainstream mobile SoC on 5nm costs $20–50. An advanced AI accelerator like the NVIDIA H100 costs approximately $3,320 to manufacture (including die, HBM memory, packaging, and test). The most complex chips like the NVIDIA GB200 superchip cost over $13,000 to manufacture.
How much does a TSMC wafer cost in 2026?: TSMC wafer costs in 2026: 3nm (N3/N3E) averages ~$19,500 per wafer (range $17,000–$22,000). 5nm (N5) averages ~$18,500 ($16,000–$21,300). 7nm (N7) averages ~$9,500 ($8,100–$10,900). 28nm averages ~$3,000 ($2,550–$3,450). Samsung 3nm is approximately 20–25% cheaper at ~$15,000 per wafer.
How much does HBM memory cost?: HBM3 costs approximately $200 per 24GB stack. HBM3E costs approximately $300 per 36GB stack. HBM2e costs approximately $120 per 16GB stack. HBM4 (next generation) is expected to cost approximately $500 per 48GB stack. HBM commands a 5–6× premium over equivalent DDR5 capacity due to 3D stacking complexity.
How much does CoWoS packaging cost?: TSMC CoWoS-S 2.5D packaging costs approximately $70 per unit for standard interposer configurations. CoWoS-L (for larger multi-die designs) costs approximately 20–40% more. Intel EMIB costs approximately $35 per unit. 3D stacking (SoIC) costs approximately $120 per unit. CoWoS lead times are 40–52 weeks as of early 2026.
What is the cost breakdown of an NVIDIA H100?: The NVIDIA H100 SXM5 has an estimated manufacturing cost of ~$3,320: logic die cost ~$300 (814mm² on TSMC 4N), HBM3 memory ~$1,350 (six stacks, 80GB), CoWoS-S packaging ~$750, plus test and assembly. NVIDIA sells the H100 at approximately $28,000, yielding a gross margin of approximately 88%.
Why are chip manufacturing costs increasing?: Three main factors: (1) EUV lithography — advanced nodes require multi-pass EUV patterning, dramatically increasing wafer cost. TSMC 3nm wafers cost roughly 6.5× more than 28nm. (2) Advanced packaging — CoWoS, HBM integration, and multi-die architectures add $500–$1,500+ per chip. (3) Memory bandwidth — AI workloads require 6–8 HBM stacks costing $1,200–$2,400 per chip. These three costs didn't exist or were negligible at older nodes.
How much does it cost to design a chip?: Chip design costs (NRE) have escalated dramatically. A 28nm chip design costs approximately $30–50M. A 7nm design costs $100–200M. A 5nm design costs $200–400M. A 3nm design costs $400–600M+. These costs include EDA tools, IP licensing, mask sets ($10–20M at 3nm), engineering headcount, and verification/validation.
What determines chip manufacturing yield?: Yield depends on die size, defect density (D0), and process maturity. TSMC 3nm has a D0 of ~0.09–0.14 defects/cm² (early vs mature production). Larger dies have exponentially lower yields — an 814mm² H100 die yields roughly 40–50%, while a 100mm² chip yields 85–95%. Yield directly determines cost per die since lower yield means fewer good chips per wafer.