Semiconductor Wafer Pricing by Process Node (2026)
As of February 2026, TSMC 300mm wafer costs range from ~$3,000 at 28nm to ~$19,500 at 3nm. Samsung offers 20-25% lower pricing at comparable nodes.
Last updated: February 2026 ·
300mm Wafer Pricing by Node and Foundry
| Node | Foundry | Avg Price |
|---|---|---|
| 3nm | TSMC N3/N3E | $19,500 |
| 3nm | Samsung 3GAE | $15,000 |
| 5nm | TSMC N5/N4 | $18,500 |
| 5nm | Samsung 5nm | $13,000 |
| 7nm | TSMC N7 | $9,500 |
| 16nm | Intel | $4,500 |
| 28nm | TSMC | $3,000 |
Prices reflect high-volume production wafer costs. Actual pricing varies by contract terms, volume commitments, and customer tier. All values in USD.
Key Trends
EUV drives exponential cost growth. The transition from DUV to EUV lithography at 7nm and below accounts for the steepest jump in wafer pricing. EUV tools cost $150M+ each and require significantly more process steps, pushing 3nm wafer costs to 6.5x the price of 28nm wafers.
Samsung undercuts TSMC by 20-25%. At comparable EUV nodes (3nm, 5nm), Samsung offers meaningfully lower wafer pricing to attract fabless customers. However, TSMC maintains higher yields and more mature process libraries, which can offset the per-wafer cost advantage when measured on a per-good-die basis.
TSMC 5nm/4nm pricing rivals 3nm. TSMC N5/N4 wafer costs ($18,500 avg) are approaching N3 levels due to multi-patterning complexity and sustained high demand from Apple, NVIDIA, AMD, and Qualcomm. The N4 variant is the workhorse node for current-generation AI accelerators.
NRE and Mask Set Costs by Node
Non-recurring engineering (NRE) costs include mask sets, design rule verification, IP licensing, and initial test development. Mask set costs alone have grown dramatically at advanced nodes due to EUV patterning complexity.
| Node | Mask Set Cost | Total NRE |
|---|---|---|
| 3nm | $15M | $22M |
| 5nm | $6.5M | $10M |
| 7nm | $3.5M | $5.5M |
| 16nm | $1.5M | $2.8M |
NRE estimates assume a full custom design tape-out. Multi-project wafer (MPW) options can reduce initial costs by 5-10x for prototyping.
Methodology
Wafer pricing data is compiled from multiple public and industry sources including TrendForce quarterly foundry reports, Morgan Stanley equity research, CSET (Georgetown) semiconductor cost models, SemiWiki industry analysis, and EEWORLD reference data.
Prices represent estimated high-volume production costs for 300mm wafers as of early 2026. Actual contract pricing varies based on volume commitments (typically 10,000+ wafer starts per year for lowest tiers), customer relationship, wafer start guarantees, and technology maturity. Spot and low-volume pricing may be 20-40% higher than the averages shown.
Samsung pricing is estimated from competitive analysis and customer disclosures. Intel foundry pricing reflects Intel Foundry Services (IFS) external customer rates. NRE and mask set figures are derived from IBS and Semiengineer cost models.
For full data provenance and terms of use, see Terms & Data Provenance.
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