AI Accelerator Manufacturing Cost (COGS)
Newest print Dec 2025Model run Mar 2026Reviewed semi-annuallyCSV — newest observations; full series with a Pro keyAPIReference page: AI Accelerator Manufacturing Cost Estimates (2026)
Logic Die: $850 (B200 (2025)) — Epoch.ai, Dec 2025 (estimate). Basis: BOM cost.
AI Accelerator Manufacturing Cost (COGS) — latest readings
15 observations across 3 series, 2020–2025.
| Series | Latest ($) | Source |
|---|---|---|
| Logic DieB200 (2025) | $850 | Epoch.aiDec 2025 |
| HBMB200 (2025) | $3,250 | Epoch.aiDec 2025 |
| Packaging & TestB200 (2025) | $2,650 | Epoch.aiDec 2025 |
Estimated manufacturing cost breakdown for NVIDIA A100, H100, H200, B200 and AMD MI300X. Shows HBM shift from 33% to 45%+ of BOM.
Logic Die: $850 (B200 (2025)), Epoch.ai, Dec 2025
Source: Silicon Analysts model, Deep Research, Epoch.ai · Basis: BOM cost
Prints ledger
| Note and copy | |||||||
|---|---|---|---|---|---|---|---|
| B200 (2025) | Logic Die | $850 | |||||
Source: Epoch.ai, Dec 2025 · Basis: BOM cost · Estimate 2×~400mm² N4P chiplets. Chiplet yield advantage. | |||||||
| B200 (2025) | HBM | $3,250 | |||||
Source: Epoch.ai, Dec 2025 · Basis: BOM cost · Estimate HBM3E. 8 stacks, 192GB. 45% of total COGS. HBM now dominant BOM component. Re-based 2026-08-16 to the Aug-2026 HBM3e contract level (~$17/GB); tracks chipSpecs.ts. | |||||||
| B200 (2025) | Packaging & Test | $2,650 | |||||
Source: Epoch.ai, Dec 2025 · Basis: BOM cost · Estimate CoWoS-L ~$1,100 + test & assembly ~$1,550. | |||||||
| MI300X (2024) | Logic DieOur model estimate | $600 | |||||
Source: Silicon Analysts / SemiAnalysis, Mar 2026 · Basis: BOM cost · Estimate 8 XCD (5nm) + 4 IOD (6nm) chiplets. | |||||||
| MI300X (2024) | HBMOur model estimate | $2,900 | |||||
Source: Silicon Analysts / SemiAnalysis, Mar 2026 · Basis: BOM cost · Estimate HBM3 192GB (8 stacks). 55% of BOM. | |||||||
| MI300X (2024) | Packaging & TestOur model estimate | $1,800 | |||||
Source: Silicon Analysts / SemiAnalysis, Mar 2026 · Basis: BOM cost · Estimate Massive CoWoS-class interposer (~5,700mm²) for 12 chiplets + 8 HBM stacks. Most complex 2.5D package in production. | |||||||
| H200 (2024) | Logic DieOur model estimate | $300 | |||||
Source: Silicon Analysts, Mar 2026 · Basis: BOM cost · Estimate Same 814mm² N4 die as H100. Identical wafer cost. | |||||||
| H200 (2024) | HBMOur model estimate | $2,400 | |||||
Source: Silicon Analysts, Mar 2026 · Basis: BOM cost · Estimate HBM3E 141GB (6 stacks 8-hi). ~$250/stack. Re-based 2026-08-16 to the Aug-2026 HBM3e contract level (~$17/GB); tracks chipSpecs.ts. | |||||||
| H200 (2024) | Packaging & TestOur model estimate | $2,450 | |||||
Source: Silicon Analysts, Mar 2026 · Basis: BOM cost · Estimate CoWoS-S packaging ~$750 + test & assembly. | |||||||
| H100 (2023) | Logic DieOur model estimate | $300 | |||||
Source: Silicon Analysts, Feb 2026 · Basis: BOM cost · Estimate 814mm² TSMC 4N. Mature yields at high volume. | |||||||
| H100 (2023) | HBMOur model estimate | $1,350 | |||||
Source: Silicon Analysts, Feb 2026 · Basis: BOM cost · Confirmed HBM3 80GB (6 stacks). 41% of COGS. | |||||||
| H100 (2023) | Packaging & TestOur model estimate | $1,670 | |||||
Source: Silicon Analysts, Feb 2026 · Basis: BOM cost · Estimate CoWoS-S packaging ~$750 + test & assembly ~$920. | |||||||
| A100 (2020) | Logic Die | $400 | |||||
Source: Deep Research (102 sources), Mar 2026 · Basis: BOM cost · Estimate 826mm² TSMC 7nm. Mature yields. | |||||||
| A100 (2020) | HBM | $1,350 | |||||
Source: Deep Research (102 sources), Mar 2026 · Basis: BOM cost · Estimate HBM2E. ~33% of BOM. | |||||||
| A100 (2020) | Packaging & Test | $750 | |||||
Provenance
Sources: Silicon Analysts (H100 Feb 2026), Epoch.ai (B200 Dec 2025), Deep Research (102 sources). NVIDIA/AMD do not disclose COGS; estimates from teardown analysis. Gross margin estimates based on analyst consensus.
Basis: BOM cost
Per-accelerator manufacturing cost (logic + HBM + packaging + test/assembly). EXCLUDES vendor gross margin, R&D/NRE, software and support — so it is NOT comparable to a street price, and margins derived from it are not company GAAP gross margin. Where only the total is externally sourced (e.g. the H100 ~$3,320, Raymond James 2023), the component split is our modeled allocation of that total, not a teardown.
Sources
- Deep Research (102 sources) (Mar 2026)
- Epoch.ai (Dec 2025)
Our derivations
- Silicon Analysts (Feb 2026)
- Silicon Analysts (Mar 2026)
- Silicon Analysts / SemiAnalysis (Mar 2026)
Suggested citation
Silicon Analysts, "AI Accelerator Manufacturing Cost (COGS)", as of Dec 2025, https://siliconanalysts.com/market-data/ai-chip-bom, retrieved October 13, 2026.
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Market intelligence on this data
All market intelligence →GlobalFoundries Lands $2B TSMC Deal to Add First U.S. CoWoS Interposer Source
Capacity: ~$2B multi-year interposer supply agreement (five-year initial term), volume production from H1 2028; CoWoS capacity reported sold out through 2026; ~$400M/year, ~6% of GF 2025 revenue ($6.79B)
Samsung HBM4 2027 Pricing Set to More Than Double
Samsung HBM blended ASP: +>100% YoY in 2027 (KB Securities); reported HBM4 asking price mid-to-high $4 per gigabit for 2027 vs ~$1.50 per gigabit for HBM3E (asking prices, not confirmed contracts); TrendForce: industry HBM blended ASP +121% YoY in 2027; HBM4 to be ~80% of Samsung HBM revenue in 2027 vs ~40% in 2026
TrendForce: 2027 HBM Blended ASP to Jump 121% as HBM4/HBM4E Mix Shifts
HBM blended ASP: +121% in 2027 vs 2026 (TrendForce, Sept 29 report); HBM share of DRAM wafer capacity: ~20% → approaching 30%; HBM4 share of Samsung HBM revenue: ~40% (2026) → ~80% (2027, KB Securities est.)
TrendForce Lifts 2027 HBM ASP Forecast to +121%; HBM4 Stack Seen Doubling to ~$1,300
HBM blended ASP: +121% YoY in 2027; 12-Hi 36GB HBM4 stack: ~$600 → ~$1,300 (+~117%); HBM share of industry DRAM wafer capacity: ~20% → ~30% by 2027
Frequently Asked Questions
- How much does it cost NVIDIA to manufacture an H100?
- The estimated total manufacturing cost (COGS) for an H100 SXM5 is approximately $3,320: roughly $300 for the 814mm² TSMC 4N logic die, $1,350 for HBM3 memory, $750 for CoWoS-S packaging, and $920 for test/assembly.
- Why is the B200 logic die cheaper than the H100 despite being more advanced?
- The B200 uses a chiplet design with two ~400mm² N4P dies (~800mm² total) instead of a single monolithic 814mm² die like the H100. Each smaller chiplet yields significantly better, driving per-die cost down to roughly $900 total for the logic despite using a more advanced node.
- What percentage of AI chip cost is HBM memory?
- HBM as a share of total BOM has grown from roughly 14% (A100) to 33% (H100) to 43% (H200) to 45%+ (MI300X). The B200 reverses this trend slightly at ~38% because its chiplet logic die is relatively cheap, but the absolute HBM cost continues to rise.