The Monopoly Premium Is Structural, Not Cyclical
ASML occupies a position in the semiconductor supply chain with no modern analog: it is the sole supplier of EUV lithography tools — equipment for which there is no alternative at leading-edge nodes. Competitors such as Nikon compete in the less-advanced DUV segment, and China's SMEE is attempting to develop domestic alternatives, but neither can credibly challenge ASML at the EUV tier within any planning horizon relevant to today's capex decisions [5]. That structural monopoly translates directly into pricing power that is durable, not cyclical.
EUV tools are priced in the range of $200M–$400M per unit, depending on configuration and generation [2][5]. High-NA EUV systems — the next step up in resolution — are understood to carry even higher initial price points before supply chain optimization reduces unit economics. This is not unusual: Low-NA EUV followed the same trajectory. The practical consequence is that any fab running advanced logic or memory must absorb these capital costs, and that absorption shows up in wafer pricing that no foundry or IDM can undercut without losing money.
ASML raised its 2026 revenue guidance to €34B–€39B, reflecting this demand durability [2][3]. The €38.8B backlog provides additional visibility. These are not speculative pipeline numbers — they represent contracted equipment orders from fabs that have already committed their own capex plans.
EUV Cost-Per-Wafer: Tracing the Lithography Bill Through the Stack
The cleanest way to understand ASML's pricing power is to trace it upstream from wafer costs. The table below maps published wafer pricing ranges across nodes, alongside the general EUV exposure at each tier.
| Node | Foundry | Wafer Price Range | EUV Exposure |
|---|---|---|---|
| 3nm (N3) | TSMC | ~$17k–$22k | High (multiple EUV layers) |
| 5nm (N5/N4) | TSMC | ~$16k–$21k | High (multiple EUV layers) |
| 7nm (N7) | TSMC | ~$8k–$11k | Limited (early EUV introduction) |
| 3nm (SF3) | Samsung | ~$13k–$17k | High (multiple EUV layers) |
| 5nm (SF5) | Samsung | ~$11k–$15k | High (multiple EUV layers) |
| 28nm | TSMC | ~$3k | None (DUV only) |
| 22/28nm | SMIC | ~$2k–$3k | None (DUV only) |
The price step from 28nm (~$3k) to 7nm (~$8k–$11k) reflects process complexity generally, but the jump from 7nm to 5nm and then to 3nm tracks closely with the addition of EUV layers. Each EUV layer adds machine time on equipment that costs hundreds of millions of dollars and requires significant maintenance and operational overhead. Fabs do not absorb that cost — they pass it through wafer pricing.
For a chip like the NVIDIA H200 SXM5, manufactured on TSMC's 4N process (a derivative of N5), the ~$19k per-wafer cost is one of the largest single inputs before HBM and packaging are added. The estimated total manufacturing cost of ~$5,150 breaks down approximately as follows:
| Cost Component | Estimated Amount |
|---|---|
| HBM3e (141GB) | ~$2,400 |
| Advanced packaging (CoWoS) | ~$750 |
| Wafer-level costs (logic die, lithography depreciation, etc.) | remainder (~$2,000) |
| Total mfg cost | ~$5,150 |
This illustrates how EUV tool economics permeate the bill of materials for every leading-edge AI accelerator. Procurement teams evaluating total system cost cannot treat wafer price as an isolated variable; it is downstream of ASML's pricing floor.
For a deeper look at how these component costs interact across AI accelerator generations, the Chip Cost Calculator allows direct modeling of wafer, HBM, and packaging inputs by node and configuration.
Memory Fab Economics: The Underappreciated EUV Demand Vector
Public attention on ASML's order book tends to focus on logic fabs — TSMC, Intel, Samsung's foundry — because AI chip demand is the most visible near-term driver. But memory is increasingly consequential as an EUV demand vector, and it operates under different economics.
DRAM producers are deploying EUV at the 1a and 1b nodes, with 1c-node processes expanding EUV layer counts further. SK Hynix and Samsung are both investing in EUV-intensive DRAM for HBM4 production. This is a structural shift: DRAM was historically a DUV-only domain, and the move to EUV layers represents a fundamental change in the lithography TCO profile for memory fabs.
The implication for memory fab economics is significant. DRAM wafer pricing at advanced nodes is materially higher than at legacy nodes, reflecting exactly the same EUV depreciation pass-through that applies in logic. As HBM stack counts and capacity grow — driven by AI accelerator demand — the embedded EUV cost in each HBM unit rises in parallel. This connects ASML's pricing power directly to HBM cost trajectories, which in turn flow into AI accelerator manufacturing costs like those outlined above.
ASML's 2026 EUV shipment guidance, as discussed in our prior analysis ASML EUV Shipments 2026: Memory Fab Adoption, High-NA Ramp, and What the Guidance Hike Really Signals, reflects this broadening customer base. Memory is not a secondary consideration in ASML's demand model — it is a structural pillar.
High-NA and the Next Capex Compression
ASML's 2026 gross margin guidance of 51%–53% is notable precisely because it is not higher [2]. The company explicitly cited the introduction of High-NA EUV machines as a factor moderating margins while manufacturing processes and supply chains are optimized. This is a technically honest signal: new generations of complex capital equipment carry higher unit costs and lower initial yields in production, compressing margins until the learning curve matures.
For fabs evaluating High-NA adoption, the economics are not simply about the tool price. The lithography TCO includes:
- Tool acquisition cost: The capital outlay per unit, which for High-NA is understood to be above the $200M–$400M range of established Low-NA EUV.
- Throughput ramp: Early High-NA tools operate at lower wafers-per-hour than mature Low-NA systems, increasing effective cost per wafer during the qualification and ramp period.
- Process integration complexity: High-NA tools have a smaller depth of focus, requiring tighter process window management and potentially more process development investment.
- Facility requirements: High-NA tools have larger physical footprints and different facility infrastructure requirements, adding to the real-estate and utility capex burden.
Fabs that move early on High-NA absorb higher TCO in exchange for process capability at the leading edge. Those that wait benefit from a more mature supply chain but risk falling behind on node transitions. This is the same tradeoff that played out with Low-NA EUV adoption — and the fabs that moved early on Low-NA now have the yield and process knowledge advantages that are visible in TSMC's production economics today.
For fabs and chipmakers modeling the capex implications of node transitions, the Cost Bridge tool provides a structured framework for comparing process node economics across foundry options.
Capex Concentration and the TSMC-ASML Feedback Loop
TSMC's 2026 capex guidance of $52B–$56B is the highest in the company's history [3]. That figure is the most direct leading indicator for ASML's near-term shipment schedule, because a substantial portion of advanced fab capex flows to lithography tools. When TSMC commits to that level of capital spending, ASML's order book does not merely benefit — it is structurally compelled to expand, because no advanced fab can be built or scaled without EUV tools.
This feedback loop has strategic implications beyond the two companies. Intel's capex trajectory and Samsung's foundry investment pace are secondary nodes in the same system. When Intel pauses or redirects capex, ASML's shipment timing shifts. When Samsung accelerates HBM4 and advanced foundry capacity simultaneously, the demand on ASML's production capacity compounds. ASML is running what is effectively a constrained production system for some of the most complex machines ever manufactured — and its customers have no alternative but to queue.
For context on how hyperscaler AI capex ultimately flows through to foundry and equipment demand, see our analysis of The Hyperscaler Capex Wall: $434B of Buyer-Side AI Spend, the Depreciation Lag, and Why Big Tech Borrows. The linkage from hyperscaler infrastructure budgets to ASML's backlog is real and traceable, even if the transmission mechanism runs through multiple supply chain steps.
ASML's raised 2026 guidance to €34B–€39B, combined with the €38.8B backlog and analyst consensus skewing heavily toward Buy ratings with an average 12-month price target around $1,550 [3], reflects market recognition that the lithography monopoly is not a near-term story — it is a multi-year structural position. The ~30% EUV growth rate in 2025 followed by mid-teens growth projected thereafter suggests a long ramp, not a spike [1].
What that means for procurement and strategy teams is equally durable: ASML pricing power is not a negotiating variable. It is a boundary condition. Advanced semiconductor manufacturing economics are built around it, and any capex or product strategy that does not account for the lithography TCO floor is working with an incomplete cost model.
References & Sources
[1] Investing.com, "ASML Holds Premium Valuation as Semiconductor Capex Momentum Carries Into 2026"
[2] "ASML Earnings Clear the Way for More Gains in 2026," covering Q1 earnings and 2026 guidance update
[3] "ASML Stock (ASML) Analysis: EUV Monopoly, Earnings...," TipRanks analyst consensus and backlog data
[4] Trefis, "What To Expect From ASML In 2026?"
[5] SemiWiki, "ASML lifts 2026 forecast as surging AI chip demand boosts new orders"
[6] "Is ASML Stock a Buying Opportunity for 2026?", forward P/E and return on invested capital trajectory