TSMC 1Q26 Earnings: The Capacity-Rule Break Is the Real Story

TSMC's 1Q26 report will be summarized almost everywhere as "beat and raise, AI demand strong." That framing is accurate and also the least interesting thing that happened on the call. The numbers — $35.90B in revenue, 66.2% gross margin, full-year 2026 growth raised to above 30% — are the lagging indicator. The leading indicator is a set of capacity decisions that, read carefully, rewrite the 3nm supply picture through 2028 and tell you exactly where the binding constraint sits today.

This note walks through what mainstream coverage is likely to miss: the capacity-rule break, HBM base dies as an explicit N3 customer, the clean room bottleneck, and the margin math that implies Taiwan-only gross margins are substantially higher than the reported number.

The headline results, briefly

1Q26 revenue of $35.90B came in above the $34.6-35.8B guide, up 6.4% QoQ and 40.6% YoY. Gross margin of 66.2% beat the top end of the 63-65% guide by 120bps. Operating margin was 58.1%, and EPS reached NT$22.08, up 58.3% YoY. Return on equity was 40.5%.

For 2Q26, TSMC guided revenue of $39.0-40.2B (a ~10% QoQ midpoint, ~32% YoY), gross margin of 65.5-67.5%, and operating margin of 56.5-58.5%. Full-year 2026 revenue growth was raised to "above 30%" in US$ terms, and 2026 capital expenditure was pushed to the high end of the $52-56B range.

The capex line deserves a beat. TSMC spent roughly $101B combined across 2023, 2024, and 2025. The 2026 number alone is more than half of that three-year total. This is not a linear ramp; this is an inflection.

2026 CapEx alone exceeds the combined spend of 2023-2024.

Source: TSMC 1Q26 earnings materials, Apr 16 2026. 2026 reflects the high end of the guided $52-56B range.

TSMC just broke its own rule

The consequential passage on the call was management's acknowledgement that it was violating a long-standing operating principle. In paraphrase, C.C. Wei reminded analysts that TSMC historically does not add capacity to a node once it reaches its designed target — the playbook is to ramp the next node and migrate leading customers forward. Then he announced that the N3 family would, in fact, get additional capacity across three new sites:

1. A new N3 fab inside the Tainan GIGAFAB cluster, with high-volume manufacturing targeted for 1H27.
2. Arizona Fab 2 repurposed to N3. Construction is already complete; HVM in 2H27.
3. Japan Fab 2 shifted from mature/specialty nodes to N3, with HVM in 2028.

This is in addition to the tool conversions already underway inside Tainan, where N5 lines are being fed forward to N3 as customer demand moves. The picture that emerges is not an incremental bump on the N3 plan but a multi-site buildout that will run in parallel with the N2 ramp.

The question worth asking is why now. Three readings, not mutually exclusive:

• Leading-edge demand is outrunning N3's designed capacity even after N2 starts absorbing new tape-outs. If the pipeline for N3 is full through the 2027 timeframe and N2 is sold out on its own allocations, the only answer is more N3.
• Customers who cannot or will not move to N2 are paying to keep N3 open. Smartphone baseband and application-processor roadmaps on N3, automotive SoCs on N3 variants, and — now explicitly — HBM base dies all represent long-tail N3 demand that does not migrate to N2 on schedule.
• Post-depreciation economics on N3 are about to look very different. N3 entered HVM in 4Q22, which means the earliest equipment will be fully depreciated starting in 2027. Once that happens, incremental N3 wafers get materially cheaper for TSMC to produce. Capacity added late in a node's life behaves differently on the income statement than capacity added early.

We'll come back to the margin piece below. The practical takeaway for procurement teams is that the N3 allocation conversation in 2027-2028 is going to look very different from what the current "sold out through 2026" narrative implies.

HBM base dies on N3 is the quiet announcement

Buried in the node-mix commentary was a new line item in TSMC's list of N3 customer categories: smartphone, HPC/AI, automotive, IoT, and — for the first time called out explicitly — HBM base dies.

HBM base dies (the logic layer at the bottom of an HBM stack) have historically been produced on trailing-edge nodes. The transition to leading-edge logic for base dies has been discussed publicly for HBM4 and HBM4E; SK hynix has flagged N3 as the partner node for its HBM4E base die, and Micron has indicated a similar direction. Samsung shipped its first commercial HBM4 in February 2026 using an internal 1c DRAM stack over a Samsung Foundry 4nm base die — a different path, but pointed the same direction.

The 1Q26 call turned this from a roadmap datapoint into a capacity planning datapoint. If a material share of HBM4E volume is being built on TSMC N3, it represents a new, non-trivial slice of 3nm wafer demand that does not compete with smartphone or HPC allocations at the SoC level but does compete for the same foundry tool and clean-room capacity. The implications:

• HBM4/HBM4E ramp timing gets tied to N3 allocation timing. Any slippage in the Tainan GIGAFAB N3 ramp (1H27) or the Arizona N3 ramp (2H27) is a credible second-order risk to HBM4E volume targets in 2027.
• The "HBM supply is DRAM-limited" frame is becoming less complete. For HBM4E specifically, the base-die logic node is an additional constraint. Stacking yield and base-die yield will both matter; foundry capacity joins DRAM capacity as the gating variable.
• N3 revenue mix looks different going forward. HBM base dies are small die. They consume wafer starts the same way any other N3 customer does, but revenue per die is lower. This argues for why TSMC needs the capacity expansion — even at stable mix share, you need more wafers to absorb the smaller-die product categories.

For anyone running an HBM volume model or a foundry wafer-starts model, this is worth a line item of its own.

What mainstream coverage is probably missing

Clean rooms, not EUV

When JPMorgan's Gokul Hariharan pressed management on the binding constraint, Wei's answer was direct. The bottleneck is clean room buildout pace. Not EUV tool supply. Not land availability. Not chemicals. Clean rooms.

This matters because the industry conversation for the last two years has centered on ASML EUV throughput, High-NA allocation, and litho tool lead times. Those are real constraints — but at TSMC's current leading-edge tempo, the pacing item is the civil engineering and qualification of the physical fab shell. That is why three new N3 sites and the N2 ramp can be announced in parallel: the tool orders are underwritten by capex, but the ability to absorb those tools depends on shells being ready.

The planning implication for customers: tool-supply-based forecasts of foundry capacity are looking at the wrong variable. If you are modeling 2027-2028 leading-edge wafer starts, start with clean-room qualification milestones at each site, not litho tool availability.

The platform mix inflection that didn't get covered

HPC (which, at TSMC, means AI accelerators, data-center CPUs, and related compute silicon) reached 61% of revenue in 1Q26, up 20% QoQ. This is a record. Smartphone fell to 26%, down 11% QoQ.

HPC crossed 60% for the first time; smartphone dropped below 27%.

Source: TSMC quarterly disclosures, 2Q24-1Q26. Quarters before 1Q26 are reconstructed from prior earnings materials and are approximate for trend illustration.

This is not a new datapoint — the trend has been running for eight quarters. What changed in 1Q26 is that it is no longer possible to describe TSMC as a smartphone-centric foundry that also builds AI chips. The opposite framing is now more accurate: TSMC is an AI infrastructure foundry that also builds smartphones. Every forward-looking comment from management, from capex allocation to node roadmaps to packaging priorities, should be read with that lens first.

The secondary platform data is also worth a look: IoT at 6% (+12% QoQ), Auto at 4% (-7% QoQ), DCE at 1% (+28% QoQ), Others at 2% (+17% QoQ). Auto down 7% QoQ is a useful real-economy signal inside an otherwise AI-dominated print.

The margin math that implies a ~70% Taiwan baseline

The 2Q26 gross margin guide of 65.5-67.5% is what most coverage will fixate on. The interesting number is what sits underneath it.

Management repeated two dilution headwinds on the call:

• Overseas fab dilution: 2-3% in early stages, widening to 3-4% as more overseas capacity comes online. This reflects Arizona, Kumamoto, and Dresden ramp costs versus Taiwan baselines.
• N2 ramp dilution: 2-3% for full-year 2026, reflecting initial N2 depreciation and yield curve.

Combined, that is a 4-6% gross margin headwind already baked into the 2Q26 guide. If the reported number is 65.5-67.5% after absorbing that drag, then the implied underlying Taiwan-only gross margin is approximately 68-72%.

After stripping ~5.5pts of disclosed dilution, the Taiwan-only baseline is roughly 70%.

Source: Silicon Analysts estimate using TSMC 1Q26 guidance (66.2% actual; 65.5-67.5% 2Q26) and management-disclosed 2-3% overseas plus 2-3% N2 dilution ranges.

Two conclusions follow from that math.

First, the structural pricing power in TSMC's Taiwan operations is higher than the headline number suggests. Anyone trying to price a wafer conversation — or to benchmark what Samsung Foundry or Intel Foundry would need to charge to match TSMC on returns — is underestimating the gap if they anchor on the reported 66.2%.

Second, there is a specific accounting event coming in 2027 worth calendaring. N3 entered HVM in 4Q22, which means the earliest tranche of N3 equipment depreciates off the books in 2027 under a standard five-year schedule. Management described post-depreciation N3 margin as "generally very high." N3 is already expected to cross the corporate average gross margin in 2H26, and the post-depreciation tail is the larger, longer story.

Model these economics yourself in the Chip Price Calculator.

Quick hits the big writeups will bury

Mature node wind-downs. Fab 2 (6-inch) and Fab 5 (8-inch) are being wound down. Fab 5 had a meaningful GaN footprint. For any power-electronics design team that was sourcing GaN-on-Si from TSMC, this is a supply-chain event. Alternative GaN capacity — Vanguard, Innoscience, PSMC, Wolfspeed, external fabs — becomes more important from here.

Terafab. C.C. Wei was asked about Elon Musk's Terafab announcement and acknowledged it as a new competitive vector. He separately called Intel "formidable." The conventional reading — TSMC views Samsung, Intel, and Rapidus as the competitive set — now has a fourth name attached.

CoPoS. The CoPoS (chip on panel-level substrate) pilot line is running. Management guided that production introduction is "a couple years later." For anyone modeling advanced-packaging allocation, CoWoS remains the workhorse through at least 2027; CoPoS is a 2028+ story. That said, the commentary about potentially adding "CPU" to the AI accelerator definition "someday later" is relevant here — packaging volumes for that segment would sit on whichever technology is ready.

AI accelerator definition. Today's disclosed AI accelerator revenue bucket is narrowly defined. Management indicated the definition may expand to include CPUs. If that happens, historical "AI accelerator" revenue numbers will be restated materially higher, which will affect any model that uses that line item as a proxy for the AI slice of TSMC's book. Worth flagging in models now.

N2 status. N2 has been in HVM since 4Q25 at Hsinchu and Kaohsiung with good yield per management. This is consistent with the tone in the 4Q25 call. Apple continues to be the largest initial N2 customer; the second wave (NVIDIA, AMD, others) is on the expected 2027 timeline.

A14 on track for 2028. TSMC reiterated A14 for HVM in 2028 with the previously disclosed specs versus N2: 10-15% better speed, 25-30% lower power at iso-performance, ~20% density improvement. Nothing new, but the confirmation is the newsworthy piece — there is no slip.

Middle East. Management flagged the ongoing Middle East situation as a risk factor for specialty chemicals, process gases, and LNG supply. This is the kind of geopolitical line item that usually does not show up in earnings writeups. For supply-chain leads, it is the right cue to re-pressure-test your second and third sources on krypton, neon, and LNG-tied electricity pricing.

Compare foundry-specific allocation posture across leading-edge and mature nodes in the Fab Site Explorer or dig into the Q1 allocation snapshot in our Foundry Allocation Status report.

What we're updating on the site

The three N3 capacity decisions are load-bearing for anyone using our tools to plan. We are reflecting them as follows:

• Fab Site Explorer: Arizona Fab 2 (Phoenix P2) node mapped to 3nm with HVM 2H27. Japan Fab 2 (JASM P2) node confirmed 3nm with HVM 2028. New Tainan GIGAFAB N3 site added with HVM 1H27. Capacity curves and allocation notes updated. See the foundry allocation status page for the full Q1 2026 picture.
• HBM analysis page: HBM base dies added as an N3 demand driver in the supply-side commentary; HBM4E base-die sourcing picture updated.
• Chip Price Calculator and Cost Bridge: N3 wafer cost assumptions reviewed against the post-depreciation trajectory; no change to current-quarter defaults, but a forward scenario is worth modeling for 2027-2028.

The one-paragraph takeaway

TSMC beat 1Q26 and raised 2026 guidance, but the analytically important content was a three-site N3 expansion that breaks the company's own operating rule, a first-time callout of HBM base dies as an N3 customer, and a confirmation from Wei that clean rooms — not EUV — are the binding constraint. Layer in the 68-72% implied Taiwan gross margin, the 2027 N3 depreciation tail, and the $56B 2026 capex number, and the picture is of a company simultaneously scaling the leading edge harder than ever, resetting what "mature" N3 looks like for 2027-2028, and pulling HBM supply into its N3 allocation conversation. That is a different story from "beat and raise."

References & Sources

1. [1]
   TSMC. "1Q26 Earnings Presentation". TSMC Investor Relations. Apr 16, 2026.
2. [2]
   TSMC. "1Q26 Consolidated Financial Statements". TSMC Investor Relations. Apr 16, 2026.
3. [3]
   TSMC. "1Q26 Earnings Conference Call Transcript". TSMC Investor Relations. Apr 16, 2026.
4. [4]
   Silicon Analysts. "TSMC 2026 Growth Forecast Surges to 30% on AI & 3nm Dominance". Silicon Analysts. Jan 15, 2026.
5. [5]
   Silicon Analysts. "Foundry Allocation Status — Q1 2026". Silicon Analysts. Mar 2026.