- Which AI hardware bottlenecks are tightest right now?
- On our bottleneck board (judged 2026-10-04): CoWoS-L advanced packaging (TSMC): allocated; HBM (high-bandwidth memory): allocated; InP lasers (pump, high-power): sold out; Large ABF substrates: allocated; T-glass (low-CTE glass cloth): tight; Test equipment (ATE): balanced; TSMC N3: watch; HBM base die on foundry logic: watch. A state moves only on A evidence (a filing or the company's own words) or B evidence (two independent outlets), and every earlier state is kept.
- What are the biggest chokepoints in the semiconductor supply chain?
- The most critical chokepoints are: ASML (100% of EUV lithography), Carl Zeiss SMT (100% of EUV optics), TRUMPF (100% of EUV drive lasers), Ajinomoto (>95% of ABF substrate film), AGC+Hoya (93% of EUV mask blanks), and Japanese companies controlling >90% of EUV photoresists. These nodes have no viable alternatives and lead times of 12-24+ months. Beyond equipment and materials, TSMC controls ~90% of advanced logic chip production (<7nm), making Taiwan the single largest geographic concentration risk.
- Why is TSMC and Taiwan concentration a critical risk for semiconductors?
- TSMC produces approximately 90% of the world's most advanced chips (<7nm), serving Apple, Nvidia, AMD, Qualcomm, and Broadcom. Taiwan-based companies (TSMC + UMC) account for ~67% of all foundry revenue and ~85% of advanced packaging (CoWoS for AI chips). A major disruption in Taiwan — from natural disasters (the island sits on a seismic fault line) or geopolitical escalation — could halt production of virtually all cutting-edge processors. TSMC's Arizona fab covers less than 5% of Taiwan capacity.
- Why does Japan dominate semiconductor materials?
- Japan controls 8 of 16 major material categories including photoresists (~70% overall, >90% EUV), silicon wafers (~51% via Shin-Etsu and SUMCO), EUV mask blanks (~93% via AGC and Hoya), ABF substrate film (>95% via Ajinomoto), ultra-high purity chemicals (~70% of semiconductor HF), and EUV pellicles (~60%). This dominance stems from decades of specialization in high-purity chemical manufacturing. Japan leveraged this in the 2019 trade dispute with Korea, restricting photoresist and HF exports to Samsung and SK Hynix.
- Why is South Korea dominant in memory and HBM production?
- Samsung and SK Hynix together control approximately 71% of global DRAM production and 83% of HBM (High Bandwidth Memory) revenue (Q2 2026, Counterpoint Research). SK Hynix alone took 50% and was the sole HBM3E supplier to Nvidia for the H100 and H200. HBM is the key bottleneck for AI accelerators — every H100 requires 80GB and every B200 needs 192GB. Micron (US) is the only non-Korean DRAM producer with ~25% share. South Korea's concentration is particularly acute in HBM, which is projected to be a $25B+ market in 2025.
- Can China replace these supply chain dependencies?
- China's semiconductor equipment self-sufficiency reached ~14% in 2024, with AMEC, Naura, and SMEE in the global top 20. Progress is strongest in etch equipment (~9% global share) and CMP equipment (~11%). However, gaps remain enormous in EUV lithography (15+ years behind ASML), inspection (no KLA alternative), and EUV photoresists (10+ years behind Japan). In fabrication, SMIC holds ~6% of global foundry share but cannot produce below 7nm due to EUV restrictions. In memory, YMTC produces ~5% of global NAND but is sanctioned from accessing advanced equipment.
- What happens when a semiconductor supply chain node is disrupted?
- Historical disruptions have been severe: The 2011 Tohoku earthquake knocked 20% of global 300mm wafer supply offline for 6-18 months and disrupted BT resin (90% global supply). A single bad batch of photoresist cost TSMC $550M in 2019. The 2019 Japan-Korea trade dispute weaponized photoresist and HF exports. The 2021 Texas Winter Storm shut Samsung Austin for 6 weeks ($500M+ cost). The 2022 Russia-Ukraine conflict disrupted 50% of semiconductor-grade neon. Most fabs carry only 1-3 months of critical material inventory.
- What is the CoWoS advanced packaging bottleneck?
- CoWoS (Chip-on-Wafer-on-Substrate) is the TSMC packaging that joins HBM memory to AI accelerator logic dies, and it is the step that limits how many accelerators can ship. On its July 16, 2026 earnings call TSMC's CEO said the company's packaging capacity is "so tight that now it's limiting my customers' growth" — a rationing statement; we found no "sold out" statement in TSMC's 2026 call transcripts. TSMC's company-wide payments from customers to retain its capacity rose from NT$149.7B to NT$234.2B in Q2 2026. Our board rates CoWoS-L as allocated.