The Subsidy Arithmetic Does Not Equal Wafer Cost Parity
The CHIPS and Science Act mobilized roughly $52B in direct incentives, with the Department of Commerce deploying those funds across more than 40 fab projects [4]. The 35% investment tax credit for qualifying semiconductor capex added further leverage. But fiscal year 2026 is the final year for which Commerce receives CHIPS Act incentive funding, and the ITC requires fab construction to begin before December 31, 2026 — a hard deadline that is already sorting projects into those that will qualify and those that will not [4].
The subsidy math is meaningful. A leading-edge fab carrying a $14B-$27B construction price tag can absorb several billion dollars in federal support and still leave a material cost gap versus Asian alternatives. The structural problem is that building a leading-edge fab in the US costs roughly 40-50% more than an equivalent facility in Taiwan or South Korea, by most industry estimates [1][2]. Raw materials cost per wafer at TSMC's Arizona facility runs approximately 2x the equivalent at TSMC's Taiwan fabs; labor costs per wafer show a similar doubling [6]. Utilities costs, notably, are roughly comparable — one of the few input categories that does not carry a US penalty [6].
The consequence: CHIPS Act subsidy allocation can shift the capex burden toward federal and state balance sheets, but it does not compress the per-wafer operating cost gap. Procurement teams modeling the total cost of domestic sourcing need to account for that delta explicitly. The US-Taiwan $500B framework deal, which encompasses roughly $250B in direct investment and ~$250B in credit guarantees aimed at onshoring advanced node capacity, is expected to translate into a 25-40% increase in wafer costs from the resulting US-based fabs relative to Taiwan-sourced equivalents [2]. That is the price of geographic resilience.
Raw materials and labor costs per wafer are roughly 2x higher in Arizona than Taiwan; utilities are the sole cost-equivalent input
Source: TSMC fab cost comparison data, cited in [6]
For a deeper look at how geographic capex decisions are being structured as risk arbitrage rather than efficiency plays, see our prior analysis: Capex Geography: Why the US/Japan/Korea Fab Race Is More About Risk Arbitrage Than Efficiency.
Taiwan Fab Repatriation Risk and the Ecosystem Completeness Problem
The Taiwan fab repatriation risk conversation often focuses on the wafer fabrication step, but the more immediate supply chain vulnerability lies upstream and downstream of the fab itself. TSMC's Arizona facility illustrates the gap clearly: chips produced there are currently routed back to Taiwan for packaging, dicing, and testing because domestic advanced packaging infrastructure does not yet exist at scale [6]. Amkor's US facility, targeted to support TSMC Arizona's advanced packaging needs, is not expected to reach operational readiness until around 2028 [6].
This is not a minor logistics footnote. CoWoS packaging — the substrate technology underpinning NVIDIA's H100, H200, and Blackwell-series accelerators — runs roughly $50-$90 per unit under current capacity constraints. The absence of that capability in the US means that even chips fabricated domestically re-enter the Asian supply chain for a critical assembly step. A Taiwan Strait disruption scenario that grounded that return shipment would interrupt supply even from nominally "US-made" chips. Strategic planners modeling Taiwan fab repatriation risk need to scope the problem at the full supply chain level, not at the wafer fab level alone.
The ecosystem immaturity problem extends further: local tool-service networks, specialty chemicals supply chains, and the trained technician base that Asian fabs have accumulated over decades are not replicated overnight [1]. These are the inputs that drive yield and cycle time, and their absence is one reason TSMC founder Morris Chang's assessment — that Arizona operations would be less efficient than Taiwan equivalents — has been borne out by early operational data [6].
For context on how lithography equipment constraints compound these dynamics, see our coverage of EUV shipment allocation: The Lithography Chokepoint: ASML EUV Shipment Ramp, High-NA Economics, and the Geopolitical Reordering of Foundry Equipment Allocation.
Intel 14A: The Highest-Stakes Foundry Play in the US
Intel's 14A node represents the only US-headquartered attempt to build a leading-edge foundry business targeting external customers at gate-all-around geometry. As a foundry play, it carries weight that goes beyond Intel's own product roadmap: if 14A reaches competitive yield and cycle times, the US would have a credible non-TSMC advanced process option for the first time in a decade. If it does not, the domestic advanced foundry landscape defaults to TSMC Arizona — a US-located but Taiwan-operated facility.
The Intel 14A foundry play faces a compounded challenge. Intel must simultaneously fix its own manufacturing execution track record, attract external customers who are already qualified on TSMC's N3/N5 processes, and do so in a cost environment where, as noted above, US fab operating costs run materially above Asian benchmarks. Wafer pricing at Intel's US fabs sits at roughly $5k-$8k per wafer at the Intel 7 node — competitive with TSMC's 7nm at ~$10k, but facing a different competitive dynamic at leading edge, where TSMC's N3 commands ~$20k and Intel 14A will need to price relative to that benchmark [see Chip Cost Calculator].
The CHIPS Act subsidy framework is a meaningful input here: Intel has been among the largest recipients of CHIPS Act award commitments. But subsidy dollars reduce capex payback periods; they do not automatically produce competitive yields. The external foundry customer base that Intel needs to validate 14A — hyperscalers and fabless AI chip designers — will qualify on technical merit and supply reliability, not on geopolitical goodwill alone.
For analysis of the startup ecosystem building around Intel's foundry licensing model, see: Terafab, Intel 14A, and the New US Fab Startup Playbook.
Micron US Fab Strategy and Korea Fab Subsidy Competition
Micron's domestic 300mm investment trajectory reflects a deliberate strategic posture: US fab capacity is being built for supply chain resilience and US government procurement qualification, not for wafer-cost parity with Asian production. SK Hynix's planned US listing — potentially raising up to ~$14B — signals that memory makers broadly are treating geographic diversification as strategic insurance [1]. Neither Micron nor SK Hynix is modeling US fabs as their low-cost production base; that role remains with established Korean and Taiwan operations.
Korea fab subsidy competition adds a further dimension. South Korea has its own domestic incentive programs for semiconductor investment, and the competition for capital between US and Korean subsidy regimes creates a dynamic where memory makers can credibly negotiate with multiple governments simultaneously. For procurement and strategy teams, the implication is that memory supply from US-domiciled fabs will carry a cost premium relative to Korean-origin product — a premium that may be acceptable for defense, government, or supply-chain-resilience-rated procurement categories but that requires explicit justification in commercial cost models.
The critical materials dimension sharpens the picture further. Tungsten — essential for semiconductor interconnects — is emerging as a supply chain bottleneck with concentrated sourcing geography, adding another layer of input cost and supply security risk that neither subsidies nor geographic fab diversification fully addresses [3]. Energy security adds additional uncertainty in a global environment where commodity inputs to fab operations face geopolitical exposure [3].
| Cost/Capacity Metric | Taiwan / Korea Fabs | US Fabs (Est.) |
|---|---|---|
| Fab construction cost premium | Baseline | ~40-50% above baseline [1][2] |
| Raw materials cost per wafer (5nm) | ~$1,520 | ~$3,040 [6] |
| Labor cost per wafer (5nm) | ~$1,800 | ~$3,600 [6] |
| Utilities cost per wafer (5nm) | ~$630 | ~$630 [6] |
| Expected wafer cost premium (US vs Taiwan) | Baseline | ~25-40% above baseline [2] |
| US share of global fab capacity (1990) | ~37% US | — [4] |
| US share of global fab capacity (2022) | ~10% US | — [4] |
The Import Gap and the Strategic Calculus Through 2030
The aggregate import data underscores how far domestic production lags domestic demand. US chip imports reached nearly $90.5B in the first eight months of 2026 — approximately 1.8x the ~$49.2B imported over the same period in 2025 [5]. Semiconductor exports have risen by over $10B year-over-year in 2026, evidence of genuine domestic sector growth, but the import trajectory is being driven by AI data center build-out demand that domestic fabs cannot yet satisfy [5]. The US is, paradoxically, becoming more reliant on foreign semiconductors precisely because the AI infrastructure investment cycle is running faster than the domestic fab construction cycle.
The strategic calculus for decision-makers is not binary between full domestic sourcing and full offshore sourcing. The realistic path through 2030 involves a tiered supply chain: leading-edge AI accelerator production concentrated at TSMC Arizona and, if 14A delivers, Intel's US fabs; mature-node and specialty process production at a broader set of domestic facilities enabled by CHIPS Act funding; and continued reliance on Asian production for cost-optimized, non-strategic-threshold procurement. The efficiency tax is real, quantifiable, and should be modeled explicitly — not absorbed as an unexamined cost of geopolitical compliance.
For current AI hardware procurement dynamics and prepayment structures, see: Who Is Prepaying for AI Chips? The AI Hardware Bottleneck Map, October 2026.
References & Sources
[1] Silicon Analysts, "Capex Geography: Why the US/Japan/Korea Fab Race Is More About Risk Arbitrage Than Efficiency," /analysis/micron-samsung-sk-hynix-us-fab-capex-subsidy-war-2
[2] "US-Taiwan $500B Deal and Chip Supply Chains to 2030," industry analysis circulated 2025-2026.
[3] Sourceability, "Geopolitics Are Reshaping Semiconductor Supply Chain Risk in 2026," April 3, 2026.
[4] Legis1 / Congressional Research Service, "CHIPS Act Funds 40 Fab Projects, Faces 2026 Deadline," citing CRS report on US fab capacity share, 2025-2026.
[5] "The AI Data Center Build-Out Has Made the US More Reliant Than Ever on Foreign Semiconductors," citing US trade deficit figures through August 2026 and Semiconductor Industry Association 2026 State of the US Semiconductor Industry report.
[6] "Smothering Heights" fab cost comparison analysis, TSMC Fab 18 (Taiwan) vs. Fab 21 Phase 1 (Arizona), 5nm node wafer economics, 2025.