The Long March Through Lithography: China's Equipment Push, Capex Reallocation, and the Limits of Localization

The Lithography Chokepoint Is Holding — But Not Everywhere

The global semiconductor equipment market has long been defined by a single structural asymmetry: ASML manufactures every EUV lithography system sold commercially, and no credible alternative exists in production anywhere in the world. That monopoly has made EUV export controls the sharpest tool in the US-led technology restriction framework. But fixating on EUV as the sole metric of China's localization progress systematically understates what is happening across the rest of the equipment stack.

According to Yole Group's Mainland China Semiconductor Equipment Industry 2026 report published in May 2026, Chinese domestic suppliers have achieved meaningful and growing share specifically in etch, deposition, chemical mechanical planarization (CMP), and wafer cleaning — four of the five highest-volume process steps by tool count in a mature-node fab [2]. AMEC is consistently cited as China's strongest domestic etch equipment supplier, and ACM Research Shanghai has established genuine commercial traction in wafer cleaning and electrochemical processing [3]. These are not prototype demonstrations; they are tools installed in production fabs generating revenue.

This matters strategically because the economics of equipment localization are not uniform. A DUV lithography machine remains an import. But if a Chinese fab can source etch, deposition, CMP, and cleaning domestically, the import dependency per wafer step — and the associated foreign-exchange and supply-chain exposure — falls substantially. For mature nodes where lithography is less frequently the yield-limiting step, this partial localization meaningfully de-risks the production process.

SMEE (Shanghai Micro Electronics Equipment) remains central to China's domestic photolithography strategy and is the named vehicle for DUV development efforts [3]. Independent technical forecasts, however, are sobering: one rigorous methodology pegs China's earliest viable EUV capability at 2038, with an upper bound extending to 2044, based on historical gaps in EUV development timelines [5]. A recently published EUV patent from a domestic lithography firm in China — covering EUV radiation generators and lithography equipment — is a real signal worth tracking, but the distance between a patent filing and a commercially viable, yield-qualified production tool is measured in years of wafer-level learning, not months [6].

For corporate procurement and strategic planning purposes, the operative assumption should be: DUV-accessible nodes (28nm and coarser, with limited 14nm capability) are addressable by domestic photolithography over the next five years; EUV-dependent nodes (sub-7nm at scale) are not.

China Fab Capex Reallocation: Securing the Permitted Stack

The export control environment has produced a counterintuitive near-term outcome for ASML's DUV business. As noted publicly, ASML reported its DUV sales into China were stronger than expected in 2025, precisely because Chinese fabs were accelerating procurement of tools they could still legally import — both to expand capacity and to build buffer stock ahead of potential future restrictions [1]. This is rational procurement behavior under uncertainty, and it has sustained ASML's China revenue in the near term even as the long-term trajectory points toward displacement.

More broadly, Chinese fab capex is being reallocated along two vectors simultaneously. The first is capacity expansion at mature nodes (28nm, 40nm, and above), where domestic tool availability is highest and end-market demand — automotive, industrial, consumer IoT, and inference-optimized AI edge devices — is substantial. The second is an aggressive push to qualify and integrate domestic equipment at more advanced nodes, with Zhejiang Province having formally targeted 7nm to 3nm capability development over a five-year horizon as of January 2026 [4].

The wafer economics at the mature-node tier are worth grounding concretely. SMIC's 28nm process carries an estimated wafer cost of ~$2k per 300mm wafer, compared to ~$18.5k for TSMC's N5 node and ~$9.5k for TSMC's N7. That cost differential — roughly 9x between SMIC 28nm and TSMC N5 — is what makes the mature-node tier commercially viable for a domestic AI inference chip strategy, even at meaningfully lower transistor density and compute efficiency per die area.

SMIC 28nm wafer costs are roughly 9x below TSMC N5 — the foundation of China's mature-node inference chip economics

Source: Silicon Analysts Canonical Data

Source: Silicon Analysts Canonical Data

AI Accelerator Localization: The Sipeed DGX Spark Signal

The most visible system-level evidence of China's AI accelerator localization push is the emergence of products positioning themselves directly against the NVIDIA DGX platform. The Sipeed DGX Spark ecosystem represents a class of domestically assembled AI compute systems built around locally sourced or locally designed silicon, targeting inference workloads at the edge and in private-cloud deployments where NVIDIA hardware access is restricted or supply-constrained due to export controls.

These systems are not competitive with NVIDIA's H200 or Blackwell-class hardware on raw training throughput — the manufacturing economics alone explain why. An NVIDIA H200 SXM5 carries an estimated manufacturing cost of ~$5,150, broken down across three primary cost centers: the logic die on TSMC N5 (wafer cost ~$18,500 per 300mm wafer), HBM3e memory at ~$2,400, and CoWoS packaging at ~$750. A domestically produced inference accelerator on SMIC 28nm, using conventional packaging and no HBM stack, can reach the market at a fraction of that bill of materials — but at commensurately lower memory bandwidth and compute density.

The strategic logic is not parity — it is sufficiency. For inference serving of models below a certain parameter threshold, particularly quantized or distilled models optimized for domestic deployment, a domestic AI accelerator at mature-node economics is a viable procurement decision for a Chinese enterprise buyer who cannot access NVIDIA's restricted SKUs. TrendForce projects that domestic chips will reach approximately 50% of China's AI chip market in 2026 [4]. That figure should be read carefully: it reflects market share in units or value within China's addressable AI chip market, not parity with global leading-edge hardware on performance metrics.

For a deeper look at how AI chip procurement decisions are being restructured by export controls on both sides of this divide, our analysis of the US export control architecture for AI chips and China's AI chip bifurcation dynamics provide the policy and supply-chain context.

The Process Integration Problem Is the Real Moat

Equipment availability is a necessary but not sufficient condition for advanced-node production. The deeper constraint — one that is harder to transfer, acquire, or replicate on an accelerated timeline — is process integration knowledge: the accumulated, wafer-level learning that determines how individual tools interact across hundreds of process steps to produce consistent, high-yield die.

This is why the signal most worth monitoring is not SMEE press releases or patent filings, but actual fab adoption rates of domestic photolithography tools at SMIC and other leading Chinese fabs. As one independent forecast framework notes explicitly, if SMIC genuinely integrates domestic lithography machines into volume production processes, that constitutes a qualitatively more significant signal than any equipment announcement — because it means real yield data is accumulating on real wafers [5].

Zhejiang Province's five-year plan targeting 7nm to 3nm chip and equipment development also includes compound semiconductor materials, photoresists, specialty gases, and high-purity sputtering targets [4] — an acknowledgment that lithography is only one of several materials and chemistry dependencies that currently remain import-dependent. The supply chain for a leading-edge fab is not a single chokepoint but a matrix of interdependencies, and the localization effort must advance across that entire matrix to achieve genuine self-sufficiency.

For procurement teams evaluating Chinese supplier qualification risk over a three-to-five-year horizon, our Fab Site Explorer provides current node availability and equipment sourcing profiles by fab, and the Chip Cost Calculator allows direct modeling of mature-node vs. advanced-node economics for specific die geometries.

What This Means for Strategic Planning

Three structurally durable conclusions emerge from the current data:

First, the EUV gap is the ceiling, not the wall. Chinese fabs will continue to expand competitively at 28nm and above, with incremental progress toward 14nm and 7nm using multi-patterning DUV — a path that is slower, more expensive per equivalent feature, and yield-constrained, but not impossible. Sub-7nm at scale requires EUV, and that capability is not arriving before 2038 under the most optimistic credible forecast [5].

Second, equipment localization is a genuine and accelerating structural shift at mature nodes. The Yole data [2] and the supplier profiles of AMEC, ACM Research Shanghai, and others [3] document real commercial traction. Companies that supply process equipment to Chinese fabs or compete with Chinese equipment vendors in third-country markets should already be modeling share erosion in etch, deposition, CMP, and cleaning segments.

Third, the AI accelerator localization trend has crossed the 50% domestic share threshold in China's own market per TrendForce [4], which means the domestic ecosystem is large enough to sustain ongoing investment, improvement cycles, and software stack development — creating compounding advantages that are distinct from raw hardware performance comparisons.

For a comprehensive view of how allied-country capex and subsidy strategies are responding to these dynamics, see our analysis of US domestic fab ecosystem competition under the CHIPS Act and the ASML EUV economics and geopolitical reordering piece.

References & Sources

[1] China Starts Building DUV Machines — ASML's Chip Monopoly Is CRACKING, video analysis, published 2026-08-30. Referenced for ASML DUV China sales commentary and Chinese fab equipment procurement behavior.

[2] Yole Group, Mainland China Semiconductor Equipment Industry 2026, May 2026. Referenced for equipment market expansion, localization by segment (etch, deposition, CMP, cleaning), and market trajectory.

[3] JUNR-Wuxi Junr Technology / industry survey, Top 10 Chip Equipment Manufacturers in China in 2026, 2026. Referenced for AMEC etch leadership, ACM Research Shanghai cleaning capabilities, and SMEE photolithography positioning.

[4] Center for Strategic and International Studies (CSIS) / industry sources, China's Localization Drive in Semiconductors Gains Impetus from Allied Chip Export Controls, 2026. Referenced for TrendForce 50% domestic AI chip market share projection for 2026 and Zhejiang Province five-year node development targets.

[5] Independent technical forecast, A forecast of Chinese DUV and EUV photolithography progress, referenced methodology producing 2038–2044 EUV capability range and commentary on fab adoption as the key signal to monitor.

[6] South China Morning Post / industry reporting, Chinese chip making shows progress with new EUV patent from domestic lithography champion, 2026. Referenced for EUV patent filing (March 2023 filing, published 2026) from domestic Chinese lithography firm, pending CNIPA review.