The Strategic Logic Behind China's Semiconductor Localization Push
For most of the 2010s, China's semiconductor self-reliance strategy was described by Western analysts as aspirational — a politically useful narrative with limited engineering substance. That characterization has not aged well. Since the initial Entity List actions in 2019 and the accelerating export control rounds of 2022 through 2025, China's domestic semiconductor investment has moved from incremental to structurally transformative [3].
The mechanism is straightforward. Each successive US control — covering advanced logic nodes, HBM, EUV equipment, and most recently a broader set of chip performance thresholds — has forced Chinese technology companies to confront a binary: accept permanent capability ceilings or fund the domestic supply chain to remove them. For strategically important players, the state has made the funding decision easier by treating semiconductor self-reliance as a national security mandate, not a commercial one [4].
The 15th Five-Year Plan (2026–2030) codifies this explicitly, elevating technology self-reliance to a core policy priority [4]. The practical consequence is that SMIC capex, domestic equipment procurement, and AI chip design investment are now driven by policy logic — which means they will continue even when near-term commercial returns are negative. For global supply-chain planners, this is the most important structural fact: China is not building semiconductor capacity to optimize returns; it is building it to eliminate a strategic vulnerability.
This dynamic has a direct parallel in how the US has framed its own CHIPS Act investments, and in how European policymakers are now revisiting the EU Chips Act — semiconductor nationalism has become the dominant industrial policy framework globally, not just in Beijing [6].
Where the Localization Numbers Actually Stand
China's equipment localization story is real in specific process steps and overstated as a headline. The categories where domestic suppliers have made the most credible gains are etch, chemical vapor deposition, CMP (chemical mechanical planarization), and wafer cleaning [1]. Companies including NAURA, AMEC, Piotech, and Hwatsing have taken measurable share in these segments, supported by aggressive government procurement incentives and captive demand from SMIC, CXMT, and YMTC's expanding fab footprints [1].
The category where localization remains structurally limited is photolithography — specifically EUV. ASML's EUV systems remain subject to Dutch export restrictions, and no domestic Chinese supplier has demonstrated a production-capable EUV platform. China's most advanced domestically accessible lithography is DUV-based, which constrains leading-edge logic manufacturing to roughly the 7nm-equivalent node under multi-patterning — with yield and density penalties relative to TSMC's EUV-enabled N5 and N3 processes [2].
The wafer cost implications of this constraint are significant. TSMC's N5 process runs in the ~$19k per wafer range; TSMC's N7 runs ~$10k. SMIC's N+1 and N+2 processes — which represent China's practical advanced-node ceiling — are closer to the N7 cost regime, but with materially lower yields and without EUV-enabled density. The performance and die-size consequences flow directly from that yield gap.
| Process Segment | Domestic Capability (2026) | Primary Bottleneck | Key Domestic Players |
|---|---|---|---|
| Etch | Moderate-to-strong | Tool repeatability at leading edge | AMEC, NAURA |
| CVD / Deposition | Moderate | Precursor chemistry, uniformity | Piotech, NAURA |
| CMP | Moderate | Slurry, endpoint detection | Hwatsing, NAURA |
| Wafer Cleaning | Moderate | Chemical handling at tight nodes | ACM Research |
| DUV Lithography | Limited domestic; imported | Precision optics, stage control | SMEE (early stage) |
| EUV Lithography | Not available domestically | Full system: light source, optics, controls | None |
| Advanced Metrology | Early stage | Optics, AI-based pattern recognition | Limited |
Sources: [1][2][3]
For buyers and planners modeling China's trajectory, the honest framing is this: China is building a formidable mid-node manufacturing base that will serve mature and near-leading-edge demand well, while the leading-edge logic frontier — N3 and below — remains structurally inaccessible without EUV.
The YMTC HBM Problem Is More Than a Node Problem
YMTC's ambition to develop competitive HBM — and by extension to address the YMTC HBM question that has circulated in industry circles since 2023 — deserves more precise framing than it typically receives. The narrative often reduces to: "Can YMTC access advanced DRAM nodes?" That is the wrong question, or at least an incomplete one.
HBM manufacturing requires at least three distinct capability sets beyond DRAM process node: Through-Silicon Via (TSV) formation and yield, thermocompression bonding for stacking multiple DRAM dies with microbump pitches at high yield, and an EDA and test infrastructure that can handle the full stack qualification. Each represents a separate multi-year qualification wall. SK Hynix, Samsung, and Micron spent the better part of a decade building these capabilities before achieving volume-production HBM2 [see our HBM Qualification Race analysis].
YMTC's Xtacking architecture, developed for 3D NAND, demonstrates that the organization has relevant TSV competence. However, 3D NAND TSV geometry and HBM TSV geometry differ in pitch, aspect ratio, and yield requirements. The export control environment also constrains YMTC's access to the advanced process equipment — particularly atomic layer deposition tools and metrology systems — needed to push TSV quality to HBM3/HBM3e standards [2].
For corporate procurement teams evaluating whether Chinese HBM could serve as an alternative supply source for AI accelerator builds, the practical timeline estimate from publicly available analysis suggests the gap to competitive HBM3e remains several years, and the gap to HBM4 (now entering qualification at SK Hynix and Samsung) is wider still. The SK Hynix and Samsung HBM4 readiness analysis provides the comparative qualification timeline context.
AI Chip Bifurcation: The Diverging Performance-Cost Curve
The AI chip bifurcation timeline is no longer a future scenario — it is a present operational reality for Chinese AI labs and cloud providers. Since H100-class hardware became inaccessible to Chinese buyers under US export controls, domestic alternatives have moved from proof-of-concept to deployed infrastructure. Huawei's Ascend 910B and 910C, Cambricon's MLU series, and Biren's BR100 are all in active deployment, with Cambricon's market valuation reflecting the sharpened commercial urgency of domestic demand [see our prior coverage of Cambricon's surge].
The performance gap relative to NVIDIA's current-generation hardware is real and meaningful. An H200 SXM5 carries an estimated manufacturing cost of ~$4,250, broken down approximately as ~$1,500 in HBM3e (141GB stack), ~$750 in CoWoS packaging, and the remaining balance in logic die cost on TSMC's N5 process. The H200's HBM3e stack requires access to SK Hynix and Micron supply chains that are now export-controlled for China. Domestic Chinese alternatives cannot currently replicate that memory bandwidth envelope, which has direct consequences for large-model training and inference serving [see the Inference Accelerator Wars analysis for cost-per-token implications].
The bifurcation consequence for corporate buyers operating in both markets is structural:
- Western AI infrastructure continues on the NVIDIA/AMD/TSMC axis, with performance scaling driven by HBM4, advanced CoWoS packaging, and leading-edge logic nodes — a supply chain that is increasingly US-allied in its geographic concentration.
- Chinese AI infrastructure scales on a parallel axis, with performance improvements driven by domestic node improvements at SMIC, incremental HBM-equivalent memory progress at YMTC and CXMT, and system-level co-optimization that compensates partially for hardware gaps through software and architecture.
The two curves will not converge in the near term, and the export control ratchet makes convergence less likely over time. What they create is a world in which US export controls impact is measured not just in capability denial but in ecosystem divergence — different chip architectures, different compiler stacks, different benchmark assumptions, and ultimately different cost-per-token economics for enterprises choosing which infrastructure to build on.
Supply-Chain Exposure Map for Corporate Decision-Makers
The practical question for corporate strategy and procurement teams is not whether China will achieve full semiconductor self-reliance — the honest answer from public evidence is that full self-reliance at the leading edge is unlikely within any five-year planning horizon — but rather where specific supply-chain exposures sit and how they are evolving.
Three exposure categories deserve explicit board-level attention:
Equipment and materials suppliers face the sharpest regulatory risk. Each new US control round has expanded the perimeter of restricted items, and allied controls from Japan and the Netherlands have closed the most obvious workarounds. Companies with significant China equipment revenue should be modeling continued attrition of that revenue base, not a return to pre-2019 access levels.
Mature-node component buyers face a different risk: subsidized Chinese overcapacity in 28nm and above. SMIC and its affiliated fabs are adding capacity at these nodes with state support and below-market return requirements. The pricing consequence for global buyers of MCUs, display drivers, power management ICs, and similar components may initially appear favorable, but creates supplier concentration risk and undermines the economics of non-Chinese mature-node capacity — including the fabs being built in the US, Japan, and Europe under chips-act frameworks [3][6].
AI infrastructure buyers with operations in China face the most immediate operational challenge: they cannot legally access the hardware their global counterparts use, and must either accept a performance ceiling on domestic alternatives or run a bifurcated infrastructure at real operational cost and complexity.
For those modeling the manufacturing economics of the chips at the center of this competition, our Chip Cost Calculator supports scenario analysis across TSMC and Samsung node options, CoWoS and alternative packaging architectures, and HBM stack configurations — useful for stress-testing assumptions about where Chinese alternatives sit on the cost-performance frontier.
References & Sources
[1] Yole Group / Mainland China Semiconductor Equipment Industry 2026 — China equipment market expansion and domestic supplier localization data (NAURA, AMEC, Piotech, Hwatsing).
[2] Georgetown CSET / CNAS-adjacent public analysis — "Where China's AI chip supply chain stands in 2026" — supply chain bottleneck mapping from design through packaging.
[3] CSIS — "China's Localization Drive in Semiconductors Gains Impetus from Allied Chip Export Controls" — policy and equipment localization framing.
[4] Global X / 15th Five-Year Plan policy documentation — technology self-reliance as core national strategy (2026–2030).
[5] Oplexa — "US China Chip War 2026: Export Impact on Semiconductors" — export control timeline and impact assessment.
[6] Institut Montaigne — "Semiconductor Nationalism in China and the United States, and Europe's Choices" — comparative policy scale and strategic framing.