The Real Cost of First Silicon
For fabless semiconductor startups, the tapeout is the single largest capital expenditure before revenue. Yet tapeout budgets are routinely underestimated because founders focus on the per-wafer cost while overlooking the full stack of non-recurring engineering (NRE) expenses.
This guide breaks down the true cost of a tapeout by process node, explains the economics of MPW shuttles versus full-mask runs, and provides a framework for break-even analysis that startup boards and investors actually need to see.
Cost Breakdown by Process Node
Mature Nodes (65nm - 180nm)
Mature nodes remain the entry point for most chip startups, particularly those targeting IoT, automotive MCUs, power management, and industrial applications.
- Wafer cost: $1,500 - $5,000 per wafer
- Mask set: $100K - $1M
- EDA tools: $200K - $500K/year (or use academic/startup programs)
- IP licensing: $100K - $500K (standard cell libraries, PHYs, memory compilers)
- Design team: 5-15 engineers for 12-18 months
- Total NRE: $500K - $5M
At these nodes, foundries like GlobalFoundries, UMC, and SMIC actively court smaller customers. MPW shuttle runs are widely available at $5K-$50K, making prototype iteration feasible even for seed-funded startups.
Mid-Range Nodes (7nm - 28nm)
The 7nm-28nm range serves the bulk of commercial chip production: mobile SoCs, networking ASICs, FPGAs, and edge AI accelerators.
- Wafer cost: $5,000 - $12,000 per wafer
- Mask set: $1M - $10M
- EDA tools: $500K - $2M/year
- IP licensing: $500K - $5M (high-speed SerDes, DDR PHYs, processor cores)
- Design team: 20-50 engineers for 18-24 months
- Total NRE: $5M - $30M
TSMC dominates at 7nm with N7/N6 offerings. Samsung offers competitive pricing at their 5nm (SF5) and 7nm (7LPP) nodes. Intel Foundry Services is entering this space with Intel 3 and Intel 18A.
Leading Edge (3nm - 5nm)
Reserved for high-volume products: flagship mobile SoCs, data center GPUs, and AI training accelerators. Only justified when unit volumes exceed 100,000+ annually.
- Wafer cost: $16,000 - $22,000 per wafer
- Mask set: $10M - $20M
- EDA tools: $2M - $5M/year
- IP licensing: $5M - $20M
- Design team: 50-200+ engineers for 24-36 months
- Total NRE: $30M - $100M+
At these nodes, the barrier to entry is not just cost but foundry access. TSMC allocates capacity to its largest customers first, and lead times can exceed 50 weeks.
MPW Shuttles: The Startup On-Ramp
Multi-project wafer (MPW) programs share a single mask set across multiple designs, dramatically reducing the cost of first silicon.
| Node | MPW Cost | Full-Mask Cost | Savings |
|---|---|---|---|
| 180nm | $5K-$15K | $100K-$300K | 95%+ |
| 65nm | $15K-$50K | $500K-$1M | 95%+ |
| 28nm | $50K-$150K | $1M-$3M | 90%+ |
| 7nm | $100K-$500K | $5M-$10M | 90%+ |
MPW programs are offered by TSMC (via CMP, Europractice), GlobalFoundries, and Samsung. The tradeoff: you get limited die area (typically 1-5mm² per project) and fixed tapeout schedules (quarterly or biannual).
For startups, the optimal strategy is usually: MPW for validation → engineering samples for customer qualification → full-mask for production.
Break-Even Analysis
The most critical question for investors: how many chips do you need to sell to recoup NRE?
Formula: Break-even units = Total NRE / (ASP - Variable cost per unit)
Example: Edge AI Accelerator at 16nm
- Total NRE: $8M (masks, IP, EDA, design team)
- Variable cost per chip: $15 (wafer + packaging + test)
- Target ASP: $45
- Break-even: 267,000 units
Example: IoT Controller at 65nm
- Total NRE: $2M
- Variable cost per chip: $3
- Target ASP: $8
- Break-even: 400,000 units
Example: AI Training GPU at 5nm
- Total NRE: $50M
- Variable cost per chip: $3,500
- Target ASP: $15,000
- Break-even: 4,348 units
Use the Chip Cost Calculator to model your specific scenario with real wafer pricing data.
Advanced Packaging Considerations
Modern chip designs increasingly require advanced packaging, which can significantly impact unit economics:
- Standard flip-chip BGA: $5-$20 per unit — baseline for most chips
- Fan-out wafer-level packaging: $15-$50 per unit — common for mobile SoCs
- CoWoS (Chip-on-Wafer-on-Substrate): $500-$1,500 per unit — required for HBM integration
- 3D chiplet stacking: $200-$800 per unit — emerging for heterogeneous designs
For HBM-equipped AI accelerators, packaging often exceeds the logic die cost. An HBM3 stack alone costs $350-$450, and a 6-stack configuration adds $2,000-$2,700 to BOM.
Use the Packaging Model Calculator to explore packaging cost scenarios.
Foundry Selection Framework
Choosing the right foundry involves more than just node pricing:
- Node maturity: Mature nodes have higher yields and lower risk. A 28nm design at GlobalFoundries will yield better than a bleeding-edge 3nm first tapeout.
- MPW availability: Not all foundries offer shuttle programs at all nodes.
- IP ecosystem: TSMC has the broadest third-party IP catalog. Switching foundries often means re-licensing IP.
- Minimum order quantities: Some foundries require 1,000+ wafer commitments for production. Others accept 25-wafer lots.
- Geographic considerations: Export controls, tariffs, and supply chain resilience increasingly matter.
Explore foundry options with the Fab Explorer and read our Foundry Engagement Guide for a step-by-step process from NDA to production.
Recommended Next Steps
- Model your chip cost using the Chip Cost Calculator — start with a process node and die size estimate
- Run a tapeout assessment with the Tapeout Decision Workspace — compares foundry options and generates a stakeholder report
- Review the Foundry Engagement Guide at /guide/foundry-engagement — covers the practical steps from MPW shuttle to production
- Benchmark your design against existing chips using the Cost Bridge Chart
All tools are free to use. Create a free account to save your cost models and export reports.