Foundry Allocation Status Q1 2026: Where Capacity Is and Isn't

Semiconductor allocation has become a three-dimensional constraint problem. It is no longer sufficient to secure wafer starts — teams must simultaneously lock in advanced packaging slots and HBM memory supply. This analysis maps the allocation landscape across 64 fabs in our Fab Explorer, identifying where capacity exists, where it doesn't, and what that means for teams planning 2027 tape-outs.

The Allocation Landscape at a Glance

Of the 64 fabs tracked in our database, the distribution by allocation status breaks down as follows:

The headline number — 20 fabs constrained or worse — understates the severity because the constrained fabs disproportionately represent the most commercially valuable capacity. Every single fully booked fab is operated by TSMC and serves the most advanced nodes (2nm/A16) or the most critical backend packaging (CoWoS-L/CoWoS-S).

Advanced Logic: 2nm Sold Out, 3nm Severely Constrained

The three TSMC fabs producing 2nm and A16 — Fab 20 (Hsinchu), Fab 22 (Kaohsiung), and Fab 21 P3 (Phoenix) — are all fully booked with lead times of 78–104 weeks. Apple holds an estimated 50%+ of 2026–2027 N2 allocation, leaving limited slots for other customers. Pricing is rising fast, with wafer costs for 2nm expected to exceed $30,000 — a step-function increase from the ~$20,000 range for N3.

One tier down, TSMC's 3nm capacity is severely constrained across Fab 15 (Taichung), Fab 18 P4–8 (Tainan), and the under-construction JASM P2 (Kumamoto). Lead times for N3 sit at 52–78 weeks, with NVIDIA, Apple, and Qualcomm absorbing the majority of output. Hot-run premiums of 50–100% have been reported for N4/N4P at Fab 18 P1–3, where lead times range from 39–52 weeks. See the full impact of these price increases on chip costs.

The US-based TSMC Fab 21 P1 in Phoenix — a CHIPS Act beneficiary — is ramping N4/N5 production but remains severely constrained at 39–52 weeks. This facility represents the only sub-5nm capacity on US soil today, making it strategically critical for defense and hyperscaler customers with data-sovereignty requirements.

Samsung's Pyeongtaek P3 (4nm/3nm) is the only non-TSMC advanced-logic fab in the constrained tier, with lead times of 26–52 weeks and yields that remain 20–30% below TSMC at equivalent nodes. Samsung's 2nm GAA fabs — Hwaseong S3, Pyeongtaek P4, and the Taylor facility in Texas — are in early access, with volume production expected in late 2026 to 2027.

CoWoS: The Backend Chokepoint

The most acute bottleneck in the semiconductor supply chain is not wafer starts — it is advanced packaging. All three TSMC CoWoS backend fabs (AP3, AP5, and AP6) are fully booked with lead times of 52–78 weeks. NVIDIA alone holds an estimated 60–70% of total CoWoS capacity for its B200 Blackwell and H100 production.

This packaging constraint cascades upstream: even if a customer secures N3 or N5 wafer slots, the chip cannot ship without CoWoS packaging. The 10 fabs flagged with cowos_dependency in our Fab Explorer — spanning TSMC's most advanced frontend and backend lines — represent the tightest segment of the global supply chain. Explore these constraints interactively by filtering for CoWoS-dependent fabs in the allocation view.

Samsung's I-Cube and X-Cube packaging lines offer an alternative, but with lead times of 26–39 weeks and lower throughput, they cannot absorb the overflow. TSMC has also engaged Amkor's Incheon facility as a CoWoS outsource partner, but this line is itself constrained at 26–39 weeks.

HBM Supply: The Memory Multiplier

The constraint picture extends beyond foundry logic and packaging to HBM memory. Both HBM3E 8-hi and 12-hi stacks are fully allocated for 2026, with prices rising 15–22% year-over-year. SK Hynix, which holds roughly 50% of the HBM market, has indicated that shortages may extend into late 2027.

HBM4 is in early access — SK Hynix has delivered samples, with volume production targeted for late 2026 to 2027. For current-generation AI accelerators, the combination of fully booked CoWoS and fully allocated HBM3E creates a compound bottleneck that no single supply-chain intervention can resolve. Track the latest HBM pricing and supply signals.

Geographic Risk and US Resilience

The allocation data reveals a stark geographic concentration: all 12 fabs that are fully booked or severely constrained are located in Taiwan (10) or the United States (2). Every TSMC Taiwan fab carries an "elevated" geo-risk rating, reflecting geopolitical supply chain concerns that cannot be mitigated through inventory alone.

The two US-based severely constrained fabs — TSMC Fab 21 P1 and P2 in Phoenix — benefit from CHIPS Act subsidies ($6.6B in grants plus $5B in loans) and carry a "low" geo-risk rating. However, their combined capacity is modest: 20 kWSPM at P1 (ramping) and 0 kWSPM at P2 (construction, HVM 2027). Intel's 18A fabs in Arizona (Fab 42, Fab 52/62) and Ohio (Ohio One) are in early access, offering a future alternative for customers seeking US-based advanced manufacturing.

For procurement teams evaluating supply chain resilience, the "US Resilience" routing mode in the Fab Explorer highlights which chip profiles can be sourced entirely through US and allied-nation fabs — and at what cost and lead-time premium.

What This Means for 2027 Tape-Out Planning

The allocation landscape has clear implications for teams planning tape-outs 12–18 months out:

1. 2nm is off the table for new entrants. Fab 20, 22, and 21 P3 are fully booked through 2027. Teams not already in the queue should target N3E or wait for A16 volume in 2028.

2. N3/N4 requires 12+ months of advance commitment. Severely constrained capacity at 39–78 week lead times means tape-out schedules must be locked by mid-2026 for 2027 production.

3. CoWoS packaging must be secured in parallel with wafer slots. The backend is the binding constraint — explore packaging alternatives and trade-offs in the Packaging Model Calculator.

4. HBM allocation is a board-level decision. With HBM3E sold out, any AI accelerator program must have memory supply locked before committing to frontend wafer starts. Model the cost implications in the Chip Price Calculator.

5. Geographic diversification has a price. US-based fabs offer lower geopolitical risk but come with higher costs and limited capacity during ramp. The premium is worth modeling explicitly using the Cost Bridge Chart to compare US vs. Taiwan sourcing.

Explore allocation constraints yourselfOpen the Fab Explorer filtered to show constrained and fully booked fabs — see lead times, pricing trends, and geographic risk

References & Sources

1. [1]
   TSMC. "Q4 2025 Earnings Conference Call Transcript". Jan 2026.
2. [2]
   TrendForce. "Q3 2025 Global Foundry Revenue Rankings". 2025.
3. [3]
   SemiAnalysis. "CoWoS Supply Chain Deep Dive". 2025.
4. [4]
   SK Hynix. "Q3 2025 Earnings Release". 2025.
5. [5]
   Silicon Analysts. "Fab Explorer — Allocation Availability Signals". Mar 2026.