Weekly Briefing

SK Hynix reported KRW 52.58T (~$38B) in 1Q26 revenue (+60% QoQ) on flat DRAM bit growth. Mid-60% DRAM ASP expansion alone drove the quarter. Operating margin of 72% now exceeds TSMC's ~50% — the first time memory has out-earned the most advanced logic foundry. NAND bits fell 10% QoQ while ASPs rose mid-70%: the AI-inference eSSD inflection has finally arrived. The KRW 40.35T (~$29B) net profit is not a clean modeling baseline — KRW 11.5T (~$8B) of it is valuation gains and FX. The operational print is KRW 37.6T (~$27B). Balance sheet transformation matters more than the income statement: cash KRW 54.3T (~$39B), debt KRW 19.3T (~$14B), net cash KRW 35T (~$25B), and receivables ballooned from KRW 18.2T to 33.8T (~$13B → $24B) in one quarter.

TSMC reported $35.9B in 1Q26 revenue with a 66.2% gross margin — both beats — and raised full-year 2026 growth to above 30%. But the signal buried under the headlines is that TSMC is breaking its own rule against adding capacity to a mature-design node: a new N3 GIGAFAB in Tainan (HVM 1H27), Arizona Fab 2 repurposed to N3 (HVM 2H27), and Japan Fab 2 shifted from specialty to N3 (HVM 2028). HBM base dies were explicitly named as an N3 customer for the first time. The binding constraint, management confirmed under questioning, is clean room buildout — not EUV tool supply and not land.

NVIDIA holds ~80% of the AI accelerator market by revenue with $193.7B in FY2026 data center sales, versus AMD's estimated 5-7% share (~$7-8B in Instinct revenue). AMD's MI350X matches B200 on FP8 compute (4,600 TFLOPS) and exceeds it on memory (288GB vs 192GB HBM3E), but NVIDIA's software maturity delivers 50-55% MFU versus AMD's ~45%, preserving a real-world performance gap. The bigger structural threat to NVIDIA is custom silicon — Broadcom AI ASIC revenue hit $20B+ in FY2025 — not AMD.

CoWoS-S packaging costs approximately $750 per chip for H100-class designs; CoWoS-L costs $1,000–$1,100 for NVIDIA's B200 — a 47% premium driven by multi-die complexity. Chiplet architectures add 15–30% to total test cost versus monolithic SOCs due to Known Good Die testing and interposer yield losses. TSMC CoWoS capacity is expanding from ~80,000 WPM to 120,000–130,000 WPM through 2026, with NVIDIA consuming ~60% of allocation. Memory and packaging together now represent 60–70% of AI accelerator COGS — logic silicon is no longer the dominant cost.