Weekly Briefing

EDA tools have historically been treated as engineering overhead — a procurement line item, not a strategic variable. That framing is breaking down. As AI chip designs push die sizes above 1,000mm², integrate chiplet architectures, and demand multi-physics sign-off at every tapeout, the choice of design automation stack directly affects silicon cost, time-to-revenue, and foundry yield. Understanding EDA economics is now a prerequisite for any serious AI chip cost model.

The standard read on AI hardware supply — 'TSMC is adding CoWoS capacity, so the shortage will ease' — uses the wrong metric. Monthly capacity is rising fast (an estimated ~75–80k toward a 120–130k WPM target by end-2026), but it is being pre-booked faster than it comes online: an estimated 85%+ of 2026–2027 capacity is already locked, and NVIDIA alone reportedly booked more than half of the expansion. The result is that lead times stay at 52–78 weeks even as capacity nearly doubles. The metric that actually gates AI accelerator supply is the booking window — lead time over time — not instantaneous WPM, and almost no one publishes it as tracked data.

Advanced-packaging allocation, not wafer starts, is the binding constraint on AI hardware in 2026. TSMC's CoWoS lines — both CoWoS-S and CoWoS-L — are fully booked, against total 2026 demand estimated near 1.0 million wafers (up from ~370k in 2024). NVIDIA alone is estimated to hold roughly 60% (~595k wafers) and has reportedly booked more than half of TSMC's 2026–2027 CoWoS expansion; the top three customers together account for an estimated >85% of capacity. Leading-edge 2nm is booked well into 2028 and HBM is allocated through 2026. These are sourced public estimates — most trace to a single sell-side house reproduced across outlets — so every datapoint in our live tracker carries a source, date, and confidence tier.

HBM market share is not decided by fab capacity or roadmap announcements — it is decided at qualification. Samsung's ~18-month struggle to pass NVIDIA's 12-Hi HBM3E validation (April 2024 to September 2025) cost it the Blackwell cycle while Micron, a late entrant, converted early qualification into real share. HBM4 marks the first generation where all three vendors qualified at the start of the ramp, which shifts the competitive question from "who can ship?" to "who can ship at yield and price?"

Until now, asking Claude about chip manufacturing costs returned training-data approximations — best-effort guesses that drifted further from reality every month. Silicon Analysts MCP changes that: Claude now reaches into a live database of accelerator BOMs, HBM pricing, wafer costs, and packaging benchmarks while it's talking to you. The setup takes 30 seconds. The semiconductor industry just got its first AI-native data layer.