EDA Tools in the Chiplet Era: Why Synthesis, Verification, and Place & Route Are Breaking

The Structural Problem: EDA Tools Built for a World That No Longer Exists

For the better part of three decades, the dominant semiconductor design paradigm was a single large die, a single process node, and a single foundry relationship. EDA tools—synthesis engines, place-and-route solvers, and formal and simulation-based verification platforms—were architected around that assumption. The design hierarchy was vertical: RTL flowed to gates, gates flowed to a placed-and-routed netlist, and a unified sign-off environment closed timing, power, and physical verification against one process design kit (PDK) from one foundry.

That world is dissolving. The economics of monolithic scaling have forced the industry toward chiplet-based architectures, where a single product is assembled from multiple dies—often manufactured at different nodes, by different foundries, and integrated via an advanced substrate or interposer. The AMD MI300X, for example, integrates compute dies at TSMC N5/N6 with a separate I/O die at N6, achieving a total assembled footprint of ~1,725mm² across the multi-die stack with an estimated manufacturing cost around $5,300 when HBM and packaging are included. That kind of architecture cannot be sign-off-closed with a toolchain built for a single PDK.

The consequence is not merely inconvenience. It is a structural mismatch between the complexity of what engineers are being asked to build and the toolchain they have available to build it with. Understanding that mismatch is the entry point to understanding why EDA tools are both the most critical and the most under-analyzed cost center in advanced chip development [1][4].

Synthesis and Verification: Where Complexity Compounds

In a monolithic design, synthesis is conceptually bounded: one RTL, one liberty file set, one timing closure target. In a chiplet system, synthesis must now account for die-to-die interface logic that did not previously exist. Each chiplet boundary introduces a set of physical interface cells—often driven by a D2D PHY—whose timing, power, and area characteristics must be modeled accurately at the time of synthesis, even though the die on the other side of the interface may be designed by a separate team, at a separate node, with a separate PDK.

This creates a synthesis accuracy problem. If the interface model is wrong at synthesis time, timing closure at the chiplet level will be wrong. And because each additional chiplet multiplies the number of interface boundaries, the problem does not grow linearly with chiplet count—it compounds.

Verification is where the complexity becomes most acute. A monolithic SoC has one clock domain topology, one power domain map, and one physical boundary. A chiplet system has all of those problems multiplied per die, plus a new class of problems at the die-to-die boundary: latency uncertainty in the D2D link, credit-based flow control behavior that must be verified across both dies simultaneously, and power-on sequencing across dies that may be supplied by physically separate voltage regulators on the package.

Existing simulation and formal verification tools were not designed to hold multiple, heterogeneous sub-designs in memory simultaneously and verify their interaction. Teams typically work around this by abstracting the interface—creating behavioral models of adjacent dies—but those models introduce their own verification gap: if the model diverges from the actual die's behavior in an edge case, that gap does not close until post-silicon [4][6].

The EDA market is projected to grow from approximately $18B in 2026 to ~$33.5B by 2033 [2], and a meaningful share of that growth is expected to come from expanded tooling to address exactly these multi-die verification challenges. The Big-3 vendors—Synopsys, Cadence, and Siemens EDA—collectively generate an estimated ~$16B in combined revenue today across EDA tools, IP, emulation hardware, and simulation software [3]. But revenue scale does not yet mean the toolchain gap is closed.

UCIe: Standards Progress, Methodology Gaps Remain

The Universal Chiplet Interconnect Express (UCIe) standard represents the industry's most serious attempt to create a common physical and protocol interface for die-to-die links. By standardizing the PHY layer and the protocol stack, UCIe in principle allows chiplet designers to treat the D2D interface the way PCIe is treated at the board level: a known, spec-compliant interface with defined electrical parameters and a testable compliance regime.

In practice, UCIe resolves the interconnect definition problem without fully resolving the EDA methodology problem. The standard specifies what the interface should do; it does not specify how EDA tools should verify that a given chiplet implementation actually does it across all corner cases, across all process-voltage-temperature (PVT) combinations, and in combination with a UCIe-compliant die from a different vendor.

The result is that EDA vendors are building UCIe-specific verification content—reference flows, interface VIP (Verification IP), and protocol checkers—at different rates and with different scope. A design team integrating two chiplets from different vendors, using different EDA toolchains, still faces a non-trivial integration verification problem that UCIe alone does not eliminate. This is not a criticism of the standard; it is a recognition that standards define interfaces while methodology defines assurance, and the methodology work is still maturing [5].

For procurement and program management teams, the practical implication is that UCIe compliance should not be equated with verification closure. A chiplet claiming UCIe compliance has met a protocol spec; it has not necessarily been verified in the specific system context into which it is being integrated.

Place & Route: Physical Planning in Three Dimensions

Traditional place-and-route tools operate on a flat 2D floorplan. The objective function is well-understood: minimize wire length and congestion while meeting timing and power constraints, within a defined rectangular die boundary. Advanced-node P&R tools are highly optimized for this problem, and the leading commercial tools from Cadence (Innovus) and Synopsys (Fusion Compiler) are capable of closing multi-billion-gate designs at leading nodes.

Chiplet integration breaks the flat-die assumption in two ways. First, the physical planning problem now includes the interposer or substrate as an active routing resource. Signal routing across die-to-die bumps, through redistribution layers on a CoWoS interposer (which itself runs approximately $50–90 per unit at the packaging level), and into the receiving die's bump array is a multi-layer, multi-material routing problem that P&R tools were not designed to own end-to-end. See our Advanced Semiconductor Packaging Costs analysis for the full packaging economics context.

Second, thermal and power integrity constraints in a stacked or co-packaged multi-die system require the P&R tool to reason about heat dissipation and IR drop across a physical stack that spans multiple dies and package layers. A compute die positioned adjacent to a high-power I/O die on an interposer will experience a thermal environment at runtime that differs from what a per-die thermal simulation would predict. Getting that right during P&R requires co-simulation between the physical design tool and the package-level thermal/power solver—a workflow that is improving but not yet seamless across the major tool platforms [1][4].

EDA Spend as a First-Order Cost: What the Numbers Imply

The semiconductor industry has historically treated EDA as a necessary overhead cost, a line item in R&D budgets that scales with headcount rather than with silicon economics. That framing is increasingly inadequate for advanced chiplet programs.

With EDA vendor revenue estimated at roughly 12–15% of total semiconductor R&D spend when IP licensing is included [3], the EDA investment for a leading-edge AI accelerator program is not marginal. Consider the following cost benchmarks for representative AI accelerator designs:

Note: Mfg cost includes HBM and packaging. H100 SXM5 breakdown: HBM ~$1,350, packaging ~$750. B200 breakdown: HBM ~$2,900, packaging ~$1,100. MI300X breakdown: HBM ~$2,900, packaging ~$1,200.

The MI300X's multi-die architecture delivers a larger effective silicon area than either H100 or B200 at a lower per-mm² wafer cost by mixing N5 and N6 process nodes—but it does so at the cost of substantially greater EDA complexity. That EDA complexity is a real project cost that does not appear in the manufacturing cost estimates above. Design schedule extensions, additional emulation hardware time, and the engineering labor required to close a multi-die verification environment are costs that land in R&D P&L, not in cost-of-goods—making them invisible to supply chain analysts who focus only on wafer and packaging economics.

For teams modeling tapeout economics, our Chip Cost Calculator provides a useful baseline for the silicon and packaging components; the EDA and methodology cost layer requires separate treatment informed by program-specific complexity assessments. See also the Tapeout Cost Guide for Fabless Startups for a grounded view of how design costs stack up at different nodes.

What to Watch in 2026 and Beyond

Three developments warrant close monitoring by engineering leadership, procurement teams, and strategic planners tracking the EDA market.

First, AI-augmented EDA tools are moving from experimental to production use. Machine learning-assisted P&R, which uses trained models to guide cell placement and routing decisions, is already embedded in commercial tools and demonstrably reduces iteration cycles on well-characterized design styles. The open question is whether those models generalize to the heterogeneous, multi-PDK design environments that chiplet architectures require [6].

Second, the competitive dynamic between Cadence and Synopsys is shifting. With Synopsys having absorbed Ansys and generating approximately $8B in CY2025 revenue—substantially above Cadence's ~$5.3B—the two leaders are no longer competing solely on EDA tool performance. They are competing on full-stack simulation and verification platforms that span chip, package, and system levels [3]. How that competition resolves will determine which toolchain becomes the default for chiplet-era design closure.

Third, TSMC's EDA Alliance program—which certifies and co-develops reference flows with EDA partners for each new process node—will be a key indicator of how quickly chiplet-specific methodology gaps close at leading nodes [5]. When TSMC certifies a multi-die integration reference flow for a given node, it signals that the EDA toolchain is production-ready for that architecture. The timeline and scope of those certifications is worth tracking as a leading indicator of when chiplet design complexity becomes routine rather than heroic.

The EDA market's projected growth to ~$33.5B by 2033 [2] is not merely a reflection of more chips being designed. It is a reflection of those chips being structurally harder to design—and the tool investment required to close them rising accordingly.

References & Sources

[1] TestFlow, "Top 10 Semiconductor Design Tools (EDA Software) in 2026, Compared," 2026.

[2] Electronic Design Automation Market Size & Forecast 2026–2033, market research report, 2026.

[3] SemiAnalysis, "EDA Market Primer," 2025–2026.

[4] "What is Electronic Design Automation (EDA)? – How it Works," industry reference, 2025–2026.

[5] TSMC, "EDA Alliance," Open Innovation Platform documentation, tsmc.com.

[6] "AI-Powered EDA Tools: Transforming the Future of Chip Design," industry blog, 2025–2026.