Interactive Foundry Sourcing Kit
For Startups & Small Fabless Teams
Welcome! This guide provides a comprehensive, interactive overview of sourcing silicon from semiconductor foundries, tailored for early-stage chip companies and small fabless teams. Navigate through the sections using the sidebar to understand engagement models, choose the right process node, plan your timeline, manage costs, and coordinate logistics.
Goal: To demystify the foundry process and equip you with actionable knowledge, checklists, and tools to successfully bring your silicon innovation to life.
Foundry Engagement Models
Early-stage chip companies have several ways to work with semiconductor foundries. Here’s a visual summary:
MPW Shuttle
Best For: Prototypes, Proof-of-Concept, Academia, Very Low Volume.
Key Benefit: Lowest NRE Cost (Shared Masks).
Key Tradeoff: Fixed Schedules, Limited Wafers/Dies, Not for Production.
Access Via: Brokers (MOSIS, Europractice) or Direct Foundry Program (e.g., CyberShuttle).
Support Level: Minimal direct foundry support; rely on broker/PDK documentation.
VCA / Intermediary
Best For: Startups needing support, Low-to-Medium Volume Production, Complex Designs.
Key Benefit: Easier Access, Turnkey Services, Reduced Admin Burden.
Key Tradeoff: Added Cost (Margin/NRE), Less Direct Control.
Access Via: Engage directly with VCA partner (e.g., GUC, Alchip).
Support Level: High support from VCA for design, fab interface, logistics.
Direct Engagement
Best For: High Volume Production, Teams with Experience, Need for Full Control.
Key Benefit: Maximum Control, Potential Volume Pricing, Direct Communication.
Key Tradeoff: High Barrier to Entry, Requires Internal Expertise & Resources.
Access Via: Establish direct relationship with Foundry (requires qualification).
Support Level: Direct access to foundry sales/tech support (level varies by customer size).
Which Engagement Model Fits You?
Answer these questions to get a recommendation based on common startup scenarios.
1. Direct Foundry Engagement
Become a direct foundry customer. Requires significant upfront effort (NDAs, credit checks, audits) and often a strong business case (high volume potential, funding). Foundries often prioritize high-volume customers.
Pros: Direct communication, potential volume pricing, full transparency.
Cons: High barrier to entry for small startups, requires internal expertise, significant admin overhead.
2. Value Chain Aggregators (VCA) / Intermediaries
Work through foundry-vetted design service partners (like those in TSMC’s VCA program) who bundle smaller projects. They handle the foundry interface, design steps, mask tooling, wafer fab, packaging, and testing (turnkey ASIC services).
Pros: Easier access to leading foundries, production slot security, potential cost sharing (masks), leverages partner expertise, reduces your admin burden.
Cons: Added margin/NRE fee, less direct control, dependent on partner relationship.
Example VCA Partners & Design Services
Below are examples of companies providing VCA or ASIC design services (often partnering with major foundries like TSMC, Samsung, GlobalFoundries). This list is illustrative, not exhaustive. Always check official foundry partner lists and perform due diligence.
| Partner | Description / Focus | Key Services / Expertise | Website |
|---|---|---|---|
| Global Unichip Corp. (GUC) | Leading ASIC provider with strong ties to TSMC, known for complex designs on advanced nodes. Focus on HPC, AI/ML, Networking. |
|
guc-asic.com |
| Alchip Technologies | Major ASIC vendor focusing on high-performance, large-scale SoCs (HPC, AI, Auto). Primarily TSMC processes. |
|
alchip.com |
| Faraday Technology | ASIC & Si IP provider working with UMC, Samsung, Intel. Strong in IoT, Multimedia, Networking. |
|
faraday-tech.com |
| Alphawave Semi (incl. OpenFive) | Focus on connectivity IP and custom silicon solutions, including chiplets. Acquired OpenFive. |
|
awavesemi.com |
| Synopsys Design Services (incl. Inomize) | Broad design services leveraging Synopsys IP & EDA tools. Acquired Inomize (strong in Auto, IoT, Medical). |
|
synopsys.com/services |
Note: Partner capabilities and foundry relationships change. Always verify directly with the VCA and the foundry.
3. Multi-Project Wafer (MPW) Shuttles
Share mask sets and wafer lots with other customers via foundry MPW programs (like TSMC’s CyberShuttle® service) or brokers (e.g., Europractice, MOSIS, Muse Semi). Significantly lowers prototyping NRE cost (up to 90% reduction cited).
Major foundries run shuttles for various nodes, often with frequent launches. Check specific foundry or broker schedules (e.g., TSMC CyberShuttle schedule example).
Pros: Dramatically lower prototyping cost, ideal for proof-of-concept, access via brokers often easier.
Cons: Limited wafer quantity (few dies/wafer), fixed tape-out dates, not suitable for volume production.
Finding MPW Shuttle Runs
MPW runs are offered directly by some foundries or aggregated by brokers. Schedules and node availability change frequently. Below are common providers/types:
| Provider / Service | Description | Typical Focus (Nodes/Foundries/Audience) | Schedule/Details Link |
|---|---|---|---|
| Foundry Direct (e.g., TSMC CyberShuttle®) | Direct MPW service from the foundry itself. Often requires direct customer relationship or VCA access. See example details below. |
|
TSMC CyberShuttle |
| MOSIS | Long-standing US-based MPW broker. Supports various foundries. |
|
themosisservice.com |
| Europractice IC | European platform providing access to MPW runs, tools, and training. |
|
europractice-ic.com |
| Muse Semiconductor | MPW service focused on simplifying access, particularly for universities and startups. |
|
musesemi.com |
Example: TSMC CyberShuttle® Details (Illustrative)
| Node Coverage | Wide range from mature (e.g., 0.5µm, 0.18µm, 65nm) up to advanced FinFET (e.g., 16nm, N7). Check official list for specifics. |
| Typical Frequency | Monthly or bi-monthly for popular nodes (e.g., 28nm, 40nm, 65nm). Less frequent for others. |
| Est. Samples / Run | ~40 (200mm wafers) or ~100 (300mm wafers). Varies by die size. |
| Access Method | Direct TSMC account or via approved VCA/Broker. |
Typical Run Frequency (Illustrative)
Illustrative Upcoming Tape-Out Deadlines (Example 2025)
| Node | Tape-Out Deadline | Run Name (Example) |
|---|---|---|
| 0.18um CMOS (Mixed-Signal) | Apr 28, 2025 | 180G-2504A |
| 65nm LP (Low Power) | May 5, 2025 | 65LP-2505A |
| 40nm LP (Low Power) | May 12, 2025 | 40LP-2505B |
| 28nm HPC+ (High Perf. Compute) | May 19, 2025 | 28HPC+-2505C |
| 16nm FFC (FinFET Compact) | May 26, 2025 | 16FFC-2505D |
| N7 (7nm FinFET) | Jun 2, 2025 | N7-2506A |
| 65nm LP (Low Power) | Jul 7, 2025 | 65LP-2507A |
| 28nm HPC+ (High Perf. Compute) | Jul 21, 2025 | 28HPC+-2507B |
Note: Schedules and frequency visuals are purely illustrative and may not reflect actual dates or availability. Real schedules change frequently and must be confirmed directly with the MPW provider. Current date: Sun Apr 20 2025.
Tip: Contact providers well in advance as shuttle deadlines are firm and require completed design/layout files. You typically need PDK access before targeting a specific shuttle run.
Summary: Direct vs. Broker/VCA vs. MPW
Many startups use a hybrid approach: MPW prototype (often via broker), then direct or VCA for production. Direct offers transparency/cost advantages at volume. Aggregators shield from overhead and leverage relationships. MPW minimizes initial NRE.
Overview of Foundry Process Nodes for Startups
Choosing the right node balances performance, power, cost, and NRE. Target the most mature node that meets requirements. Node names and specifics vary by foundry (TSMC examples below).
Key Node Characteristics (Estimates based on TSMC – Verify with Your Foundry)
| Node Family (TSMC Example) | Type | Maturity | Est. Mask NRE* | Est. Wafer Price (Vol)* | Key Use Cases | Pros for Startups | Cons/Challenges |
|---|---|---|---|---|---|---|---|
| 28nm / 22nm ULP/ULL | Planar CMOS | Mature (2011+) | ~$1-2 Million | ~$2,800 – $3,000 | MCUs, IoT, PMICs, AI Edge (Lower Perf) | Lowest NRE, Mature IP/Tools, Frequent MPWs, Forgiving Rules | Lower density/perf, Potential capacity crunches |
| 16nm / 12nm FFC | FinFET (1st Gen) | Mature (2015+) | ~$3-5 Million | ~$4,000 – $6,000 | Mid-range AI, Networking, FPGAs | Good Perf/Power step-up, Strong IP, Proven | Higher NRE, FinFET complexity (design/verification) |
| 7nm (N7) / 6nm (N6) | FinFET (Adv) / EUV (N6) | Established (2018+) | ~$10-15+ Million | ~$10,000 | High-perf AI, Networking, CPU/GPU | High density/efficiency, N6 easy migration from N7, MPW available | Very high NRE & design cost (~$50-75M+ total proj), Complex rules, Capacity risk |
| 5nm (N5) / 3nm (N3) | FinFET (Ext. EUV) | Cutting Edge (2020+) | ~$20-40+ Million | ~$16,000 – $20,000+ | Leading-edge AI, HPC, Mobile | Highest performance/density | Extreme NRE/Wafer Cost, High complexity/risk, Volume commits needed, Generally beyond startups |
*NRE and wafer costs are industry estimates/reports (often based on TSMC, circa 2023-2024) and can vary significantly by foundry, options, volume, and time. Always get direct quotes from your chosen foundry. Current date: Sun Apr 20 2025.
Visual Cost Comparison (Illustrative Estimates based on TSMC)
These charts provide a relative visual comparison. Absolute values vary greatly. NRE costs increase dramatically with advanced nodes, while wafer price increases are less steep but still significant.
Estimated Mask NRE Comparison
Relative NRE Cost (Illustrative)
Estimated Wafer Price Comparison (Volume)
Relative Wafer Price (Illustrative)
Detailed Node Descriptions
28nm / 22nm: Mature Planar Nodes
- Technology: Planar CMOS (non-FinFET). 22nm options (e.g., ULP/ULL) optimized for IoT/analog/RF.
- Maturity: High (Introduced ~2011+). Good yields, vast IP ecosystem.
- Est. NRE Cost: ~$1-2 Million (Mask Set).
- Est. Wafer Price: ~$2,800 – $3,000 (Volume).
- Target Apps: MCUs, IoT SoCs, PMICs, RF, some AI Edge.
- Startup Benefits: Lowest NRE, forgiving design rules, frequent MPW availability.
- Challenges: Lower density/performance vs FinFET, potential capacity crunches.
16nm / 12nm: First-Gen FinFET
- Technology: First-generation FinFET (e.g., TSMC 16FF+/16FFC, 12FFC).
- Maturity: Relatively Mature (Introduced ~2015+).
- Est. NRE Cost: ~$3-5 Million+ (Mask Set).
- Est. Wafer Price: ~$4,000 – $6,000 (Volume).
- Target Apps: Mid-range AI accelerators, Networking ASICs, FPGAs, SoCs needing perf/power boost over 28nm.
- Startup Benefits: Good balance of FinFET performance/power gains and manageable cost, strong IP ecosystem.
- Challenges: Higher NRE than planar, requires FinFET design expertise (libraries, double-patterning), more complex verification.
7nm / 6nm: Advanced FinFET
- Technology: Advanced FinFET (e.g., TSMC N7). 6nm variants (e.g., N6) add some EUV layers for density/migration.
- Maturity: Established (Introduced ~2018+).
- Est. NRE Cost: ~$10-15 Million+ (Mask Set). Total project cost $50M+.
- Est. Wafer Price: ~$10,000 (Volume).
- Target Apps: High-performance AI/HPC, advanced networking, competitive mobile SoCs.
- Startup Benefits: High density & efficiency, MPW available for prototyping, N6 offers easier migration path from N7.
- Challenges: Very high NRE & total cost, significant design complexity (EUV, timing, reliability), potential capacity allocation issues. Early foundry/VCA engagement critical.
5nm / 3nm: Cutting Edge Nodes
- Technology: Frontier FinFET with extensive EUV (e.g., TSMC N5, N3).
- Maturity: Cutting Edge (Introduced ~2020+).
- Est. NRE Cost: ~$20-40 Million+ (Mask Set).
- Est. Wafer Price: ~$16,000 – $20,000+ (Volume).
- Target Apps: Leading-edge AI/HPC, flagship mobile.
- Startup Benefits: Highest possible performance/density/power efficiency.
- Challenges: Extreme cost & complexity, generally beyond typical startup budgets/resources, large volume commitments often needed, requires deep design expertise & foundry support. Often targeted for Gen 2+ products.
Try The Silicon Budget Estimator
Visualize NRE & wafer costs instantly. Input die size and volume to compare process nodes and make informed planning decisions.
Launch Budget Estimator →
Process Node Selection Tips
- Prioritize the most mature node (from your chosen foundry) that meets technical requirements.
- Consider older nodes (e.g., 40nm, 65nm families) for analog-heavy or ultra-cost-sensitive designs.
- Factor in total project cost (Design + NRE + Wafers + Packaging/Test).
- Don’t chase the bleeding edge unless absolutely necessary and funded.
- Model die-per-wafer to understand cost impact.
Sourcing Timeline: Idea to Silicon
Typical timeline from tape-out to packaged chips is ~4-6 months, but can vary significantly based on the foundry, node, and back-end partners. Engage partners early!
Interactive Timeline Estimator
Select your estimated project start date to see a typical timeline breakdown. Durations are estimates and can vary.
Note: This Gantt chart is illustrative, based on average durations. Actual timelines depend heavily on specific project details, foundry loading, and potential delays.
Foundry Onboarding Checklist (Interactive)
Tick off items as you complete them. Progress is saved in your browser’s local storage.
Onboarding Progress
Overcoming Common Foundry Sourcing Challenges
Strategies for navigating hurdles faced by small fabless companies.
Challenge 1: Small Volume & Minimum Order Quantities (MOQs)
Problem: Need fewer chips than standard wafer lot minimums (e.g., 25 wafers).
Mitigation:
- Use MPW for prototypes.
- Discuss “mini-lots” or shared production lots with VCA/Foundry (less common).
- Design for smaller die size (more dies per wafer).
- Choose older nodes with potentially more flexible capacity.
- Budget for potentially buying the minimum even if not all dies are needed initially.
Challenge 2: Allocation Bottlenecks & Lead Time Delays
Problem: Fab capacity shortages lead to delays or de-prioritization.
Mitigation:
- Maintain accurate and consistent forecasts (builds credibility). Avoid double-ordering.
- Communicate potential needs early with foundry sales/reps.
- Consider slightly earlier tape-out if possible during tight cycles.
- Have a backup plan (e.g., secondary foundry for non-critical parts, node flexibility).
- Leverage VCA partner’s clout or pre-negotiated capacity.
- Be flexible on delivery timelines.
Challenge 3: Silent Rejection (Getting Foundry Attention)
Problem: Difficulty engaging directly with a top-tier foundry due to perceived low volume/potential.
Mitigation:
- Make a compelling case: highlight growth potential, unique tech, or filling schedule gaps.
- Use warm introductions (investors, advisors).
- Be persistent, professional, and responsive.
- Engage via a VCA partner (often the most reliable route initially).
- Consider University Shuttle programs if applicable.
Challenge 4: Managing NRE Costs and Risk
Problem: High upfront mask/design costs; risk of costly re-spins.
Mitigation:
- Invest heavily in verification (simulation, FPGA proto, formal). Use external reviews.
- Use MPW for initial test chips/IP validation.
- Include debug/test features on-chip (scan, BIST, fuse options).
- Reuse known-good, silicon-proven 3rd party IP where feasible.
- Use MPW for prototypes to drastically cut initial mask cost.
- Budget explicitly for at least one potential re-spin.
- Explore if any foundry startup programs or node incentives exist (rare).
Packaging & Logistics Coordination (OSAT)
Managing the back-end process: turning wafers into packaged chips using OSATs.
Find Potential OSAT Partners
Filter OSATs by package type or location.
1. Engage Early for Packaging Design
- Involve OSAT during chip design phase.
- Choose package type (QFN, BGA, WLCSP) considering I/O, thermal, performance needs.
- Get package design rules from OSAT (pad size, pitch, keep-outs).
- Ensure chip layout is compatible with chosen package.
2. Selecting an OSAT
- Key Factors: Package capability, location (proximity to fab?), cost, lead time, quality (ISO, IATF), support/flexibility for startups.
- Major OSATs: ASE, Amkor, JCET/STATSChipPAC, SPIL, Powertech, etc. (also smaller/specialized ones).
- Send RFI to compare options (see Templates section).
- Leverage network/VCA recommendations.
3. Wafer Shipment and Handling
- Coordinate direct shipment from foundry to OSAT (common).
- Provide OSAT as “ship-to”, handle import/export details.
- Insure wafer shipment. Shipped in specialized carriers.
- Confirm incoming material requirements with OSAT (thickness, diced/undiced, taped?).
- Provide wafer map (if sorted) and Fab-to-OSAT Handoff Brief (see Templates).
4. Assembly Process and Monitoring
- Consider a small initial engineering lot (e.g., 100 units) for first run.
- Review OSAT’s First Article Inspection report/images. Approve quickly.
- Maintain communication with OSAT engineering. On-site visit if possible.
- Be prepared for on-the-spot decisions if issues arise (e.g., bonding tweaks).
5. Testing and Yield Considerations
- Contract OSAT for final test if desired (requires test program, specs, fixture).
- Provide test inputs well in advance.
- Monitor assembly and test yields. Compare vs expected die yield.
- Investigate systematic failures (e.g., specific pin fails often).
- Collaborate with OSAT/Foundry for failure analysis if needed.
6. Logistics and Delivery
- Provide clear shipping instructions (addresses, accounts, quantities).
- Ensure proper packaging (dry pack for MSL parts, ESD).
- Receive packing list, yield reports, quality data (if applicable).
- Plan for potential qualification testing (temp cycling, HTOL) if needed for target market.
Bonus Tip: For advanced needs, explore foundry advanced packaging offerings (e.g., TSMC’s InFO/CoWoS or Intel’s Foveros), though typically higher cost and complexity than traditional OSATs.
Templates & Interactive Tools
Use these downloadable templates as starting points. Adapt them to your specific project.
Silicon Sourcing Plan Builder
Fill in key project details to generate a basic Sourcing Plan outline.
1. Silicon Sourcing Plan Template Outline
- Project Overview (Chip, Application, Node, Objectives)
- Volume & Growth Projections
- Engagement Model (Direct/VCA/Broker)
- Timeline & Milestones (Gantt Chart recommended)
- Budget & Cost Estimates (NRE, Wafer, Package, Test)
- Risk Assessment & Mitigation Plan
- Team & Resources (Roles, Responsibilities, Tools, IP)
- Appendices (Contracts, Quotes, Schedules)
2. OSAT RFI (Request for Information) Template Outline
- Company & Capabilities Overview
- Available Package Types for Your Device (Size, Pin Count)
- Packaging NRE & Unit Cost Estimates (at volumes)
- Lead Time & Throughput (Eng. Lot, Prod. Lot, MOQ)
- Wafer Requirements (Incoming form, Thinning/Dicing)
- Testing Services (Wafer Probe, Final Test, Capability)
- Quality & Reliability (Standards, Certs, FA Capability)
- Logistics & Location (Facility, Shipping, Customs)
- Support & Engineering Contact
- Pricing Structure Summary
- References/Case Studies (Optional)
- Other Services (Storage, Drop Ship, Marking)
3. Risk Checklist Template (By Category)
Use this outline or the planned interactive tool.
Project Risk Tracker
(Demo – Feature coming soon!).
- Design & IP Risks: Functional bugs, IP issues.
- Schedule Risks: Tape-out slips, Fab delays.
- Manufacturing/Yield Risks: Low wafer yield, Assembly issues.
- Supply Chain Risks: Mask revisions, Export holds.
- Financial Risks: Cost overruns, Funding delays.
- Team/Operational Risks: Personnel loss, Communication breakdown.
4. Fab-to-OSAT Handoff Brief Template Outline
- Wafer Lot Identification
- Die Information
- Known Issues / Special Instructions
- Die Preparation Details
- Package Assembly Details
- Quantity & Distribution
- Testing Instructions
- Contacts
- Attachments List
Additional Resources & References
Links and pointers to help you further in the semiconductor ecosystem.
Curated Resource Database
Search our database for specific articles, tools, or service providers.
- Major Foundries (Examples): TSMC | Samsung Foundry | GlobalFoundries | UMC | SMIC | Intel Foundry Services (IFS)
- MPW Services/Brokers: Europractice | MOSIS | Muse Semiconductor | Check specific foundry MPW programs (e.g., TSMC CyberShuttle)
- Foundry Partner Programs (Example): TSMC VCA List (Check other foundries for their partner ecosystems)
- Cost Estimation Insights (External Blogs/News – Verify Dates): Semianalysis (Blog) | Search Tom’s Hardware, AnandTech for wafer pricing trends.
- Communities/Forums: EDAboard Forums | SemiWiki Forums | StackExchange Electronics
- Industry News/Guides: Semiconductor Engineering | EE Times | AnandTech
- Standards: JEDEC (for qualification/reliability) | ISO (for quality systems)
- People: Seek mentors, consultants, or connect with other founders via relevant networks/events (e.g., GSA – Global Semiconductor Alliance).