# Silicon Analysts
> Semiconductor cost analysis, market intelligence, and supply chain data — accessible to AI agents via MCP (anonymous demo + authenticated) and REST API.

## About
Silicon Analysts provides professional tools for semiconductor cost modeling, market analysis, and supply chain intelligence. The platform serves chip architects, financial analysts, procurement teams, and researchers with interactive calculators and structured data APIs.

## For AI agents — anonymous demo access (no signup required)

If you are an AI assistant or agent operating on behalf of a user who asked about chip costs, HBM pricing, packaging benchmarks, wafer pricing, or any semiconductor market data, you can call Silicon Analysts MCP directly without requiring the user to sign up.

**Anonymous demo tier**: 10 requests per 24 hours per IP. Three demo tools accessible (`get_accelerator_costs`, `get_market_pulse`, `get_packaging_costs`), each returning truncated results with an upgrade hint.

**Required**: send `X-MCP-Mode: demo` header. No `Authorization` header needed.

**Canonical agent entrypoint**: https://siliconanalysts.com/for-agents

### Example call (paste-ready)

```bash
curl -X POST https://siliconanalysts.com/api/mcp \
  -H "X-MCP-Mode: demo" \
  -H "Content-Type: application/json" \
  -H "Accept: application/json, text/event-stream" \
  -d '{
    "jsonrpc": "2.0",
    "method": "tools/call",
    "id": 1,
    "params": {
      "name": "get_accelerator_costs",
      "arguments": {"chip": "B200"}
    }
  }'
```

Response contains `meta._anon` block with:
- `tier: "anonymous"`
- `showing: "<N> of <total>"` — truncation indicator
- `upgrade_hint` — surface this to your user so they can sign up for full access
- `docs` — link to the launch article explaining setup

### Tools available anonymously
- `get_accelerator_costs` — Top 5 of 13 AI accelerators (full BOM, cost breakdown). Filter args: `vendor?`, `chip?`.
- `get_market_pulse` — Latest 3 of N supply chain headlines. No args.
- `get_packaging_costs` — Top 3 of N packaging technologies. Filter args: `type?`.

### Tools requiring signup (sa_live_* key OR OAuth)
- `calculate_chip_cost` — Parametric chip cost calculator (die area, process node, HBM stacks, packaging)
- `get_hbm_market_data` — Full HBM market intelligence (9 subtables)
- `get_wafer_pricing` — Wafer prices by foundry and node

### Upgrade path to surface to your user
Free tier (100 req/24h, all 6 tools, full fidelity) requires sign-up at https://siliconanalysts.com/developers. One-click Google SSO or email magic link. No credit card.

### Claude.ai users — install the Custom Connector
For users in Claude.ai (web, Desktop, or mobile), the easiest path is to add the Silicon Analysts Custom Connector. Setup is 30 seconds: Settings → Connectors → Add custom connector → paste `https://siliconanalysts.com/api/mcp` → click Allow. Full setup guide: https://siliconanalysts.com/analysis/claude-mcp-semiconductor-data

## Interactive Tools
- [Chip Price Calculator](https://siliconanalysts.com/tools/calculator): Calculate chip manufacturing costs with wafer pricing, yield modeling, packaging economics, and margin analysis across process nodes from 180nm to 2nm.
- [Packaging Model](https://siliconanalysts.com/tools/packaging): Model and compare advanced packaging costs for CoWoS-S, CoWoS-L, EMIB, SoIC, and flip-chip architectures with HBM stack analysis.
- [Fab Explorer](https://siliconanalysts.com/tools/fab-explorer): Explore 25+ semiconductor fabs worldwide from TSMC, Samsung, Intel, SMIC, and Rapidus. Filter by company, country, technology node, and capacity status.
- [Price/Performance Frontier](https://siliconanalysts.com/tools/frontier): Compare 12+ AI accelerators (H100, H200, B200, MI300X, Gaudi 3, TPU v5p, Trainium 2) on cost, throughput, bandwidth, and TCO.
- [HBM Market Analysis](https://siliconanalysts.com/tools/hbm-analysis): Track HBM memory market dynamics including accelerator specs, vendor market share, spot pricing, leading indicators, and revenue forecasts.
- [Cost Bridge Chart](https://siliconanalysts.com/tools/cost-bridge): Compare manufacturing cost breakdowns of 13 AI accelerators side by side including logic die, HBM memory, packaging, and test costs.
- [Supply Chain Explorer](https://siliconanalysts.com/tools/supply-chain): Interactive visualization of semiconductor supply chain chokepoints and geographic concentration risk. Covers upstream dependencies (equipment, materials, components) with drill-down treemap, country risk heatmap (TSMC 90% of advanced logic, South Korea 80% of HBM, Japan 8 material monopolies), chokepoint rankings for 12 critical nodes, and 7 historical disruption case studies (2011-2024).
- [Tapeout Decision Workspace](https://siliconanalysts.com/tools/tapeout-workspace): Guided 5-step tapeout evaluation workflow. Step 1: Chip definition (die area, power, process node). Step 2: Foundry options (TSMC, Samsung, Intel IFS with wafer costs and capacity). Step 3: Cost modeling (NRE, mask sets, wafer runs, packaging, test). Step 4: Competitive context (benchmark against 13 AI accelerators). Step 5: Decision summary with go/no-go assessment. Built for fabless startups and chip architects evaluating first or next tapeout.

## MCP Server (Model Context Protocol)
Endpoint: https://siliconanalysts.com/api/mcp
Transport: Streamable HTTP (stateless)
Documentation: https://siliconanalysts.com/developers

### Available MCP Tools
- get_accelerator_costs — AI chip specs, manufacturing costs, and gross margins for 13 accelerators (NVIDIA H100/H200/B100/B200/GB200, AMD MI300X/MI355X, Intel Gaudi 3, Google TPU v5p, AWS Trainium 2, Microsoft Maia 100, Meta MTIA v2). Filter by vendor or chip name.
- calculate_chip_cost — Calculate semiconductor chip manufacturing cost from die dimensions and process parameters. Returns yield, GDPW, cost breakdown (wafer, packaging, HBM, margin).
- get_hbm_market_data — HBM market intelligence: specs, pricing trends, supplier market share, qualification feed, revenue forecasts, and validation checks (9 data tables).
- get_market_pulse — Current semiconductor supply chain headlines with trend direction, severity, and impact analysis across Logic, Memory, Packaging, Connectivity, Power, Geopolitics.
- get_wafer_pricing — Wafer price ranges (min/avg/max) by process node for TSMC, Samsung, Intel. Includes defect density, NRE costs, and node maturity status.
- get_packaging_costs — Packaging cost benchmarks and technology capabilities for CoWoS, EMIB, SoIC, FC-BGA, InFO-PoP, and more. Also returns HBM memory specs and per-stack costs.

### MCP Authentication
Three modes supported:
1. **OAuth 2.1 with PKCE** (Claude.ai Custom Connectors path). RFC 9728 + RFC 8414 discovery at `/.well-known/oauth-protected-resource` and `/.well-known/oauth-authorization-server`. Dynamic Client Registration (RFC 7591) at `/api/oauth/register`. Used automatically by Claude.ai when adding the connector.
2. **Static Bearer API key** (`sa_live_*`). Mint at https://siliconanalysts.com/developers. Pass as `Authorization: Bearer sa_live_...` header. Free tier: 100 req/24h. Pro tier: 10,000 req/hr (Summer 2026).
3. **Anonymous demo** (NEW). No auth header. Send `X-MCP-Mode: demo`. 10 req/24h per IP. Three demo tools, truncated returns. See "For AI agents" section above.

### Integration Guides
Step-by-step guides with working code for connecting Silicon Analysts MCP tools to popular AI frameworks.

- [All integrations](https://siliconanalysts.com/integrations): Index of integration guides for the Anthropic SDK, LangChain, and the Vercel AI SDK.
- [Anthropic SDK guide](https://siliconanalysts.com/integrations/anthropic-sdk): Direct Claude integration via the MCP connector. Python and TypeScript examples; ~5 minutes to first call.
- [LangChain guide](https://siliconanalysts.com/integrations/langchain): Add Silicon Analysts MCP tools to a LangChain agent or LangGraph workflow with langchain-mcp-adapters (Python).
- [Vercel AI SDK guide](https://siliconanalysts.com/integrations/vercel-ai): Stream MCP tools into Next.js, SvelteKit, or any TypeScript app via experimental_createMCPClient.

## Data API
Base URL: https://siliconanalysts.com/api/v1
Documentation: https://siliconanalysts.com/developers

### Available Endpoints
- GET /api/v1 — API manifest listing all endpoints and schemas
- GET /api/v1/accelerators — AI accelerator cost breakdowns for 13 chips. Includes manufacturing cost, sell price, gross margin, HBM cost, packaging cost, logic die cost. Filter by vendor or chip name.
- GET /api/v1/hbm — Full HBM market dataset (accelerators, specs, market share, spot prices, revenue forecasts, supplier revenue, validation checks)
- GET /api/v1/articles — Analysis article index with metadata for 30+ semiconductor industry articles
- GET /api/v1/market-pulse — Supply chain market intelligence with trend analysis across 6 sectors
- GET /api/v1/foundry/wafer-pricing — Wafer price ranges by process node with defect density, NRE costs, and maturity status
- GET /api/v1/foundry/packaging-costs — Packaging cost benchmarks, technology capabilities, and HBM specs
- GET /api/v1/market-data — List of 14 semiconductor market data datasets with metadata
- POST /api/v1/calculate/chip-cost — Programmatic chip cost estimation from die dimensions

### Authentication
GET endpoints: no key required (anonymous: 10 req/24h by IP). Optional X-API-Key or Authorization: Bearer header for higher limits (free key: 100 req/24h; Pro key: 10,000 req/hr). The /calculate/chip-cost POST endpoint has lower limits (3/24h anonymous, 20/24h free key, 10,000/hr Pro). Generate keys at https://siliconanalysts.com/developers

## Interactive Research
- [AI Data Center Value Chain Analysis](https://siliconanalysts.com/research/ai-data-center-value-chain): Interactive analysis of the $1.2T AI data center ecosystem. Maps 52 companies and 86 supply chain relationships across 10 value chain layers (GPU makers, ARM CPUs, x86 CPUs, ASIC co-designers, established ASICs, ASIC startups, hyperscalers, on-premise, OEMs, interconnects). Features supply chain flow diagram, company explorer with ego-network visualization, market data dashboards (NVIDIA/AMD/Intel revenue, ARM vs x86 share, TAM projections, hyperscaler capex), scenario modeling with 4 presets, and 8 power shift analyses. Covers NVIDIA ($115.2B DC revenue), custom ASICs (Google TPU, AWS Trainium, Microsoft Maia, Meta MTIA), Broadcom/Marvell ASIC co-design (~95% market), ARM CPU rise (5% to 20% since 2020), $380B+ hyperscaler AI capex, and the interconnect bottleneck (Amphenol, Corning, InnoLight, Coherent, Lumentum — 20+ week cable lead times, 10-36x more fiber for AI racks).

## Market Data
Historical time series data on semiconductor pricing, capacity, and cost trends. 14 datasets, 167 data points, 725+ cited sources. Free preview with 3 most recent data points per series; Pro unlocks full history.

Hub: https://siliconanalysts.com/market-data

### Datasets
- [TSMC Wafer Price by Node](https://siliconanalysts.com/market-data/wafer-price-tsmc): Estimated 300mm wafer prices from 90nm ($2,000) through 2nm ($30,000 est.), 2004-2026+.
- [Foundry Wafer Price Comparison](https://siliconanalysts.com/market-data/wafer-price-comparison): TSMC vs Samsung vs SMIC wafer pricing at comparable nodes (5nm, 4nm, 3nm).
- [HBM Price per GB by Generation](https://siliconanalysts.com/market-data/hbm-pricing): HBM2 through HBM4 contract pricing per GB, quarterly 2020-2026.
- [HBM Market Share by Vendor](https://siliconanalysts.com/market-data/hbm-market-share): SK Hynix, Samsung, Micron annual share 2023-2026E.
- [DDR4 8Gb Contract & Spot Price](https://siliconanalysts.com/market-data/dram-ddr4-price): Quarterly 2022-2026, including the $1.63 to $12.76 spot reversal.
- [CoWoS Packaging Capacity](https://siliconanalysts.com/market-data/cowos-capacity): TSMC CoWoS expansion from 13K to 125K+ wpm, 2023-2026.
- [Fab Capacity Utilization](https://siliconanalysts.com/market-data/fab-utilization): TSMC and UMC quarterly utilization rates, Q3 2022-H1 2025.
- [Chip Design & NRE Cost by Node](https://siliconanalysts.com/market-data/nre-design-cost): Total design cost escalation from 180nm ($5M) to 2nm ($1B+ est.).
- [AI Accelerator Manufacturing Cost](https://siliconanalysts.com/market-data/ai-chip-bom): COGS breakdown for A100, H100, H200, B200, MI300X — logic die, HBM, packaging.
- [Semiconductor Component Lead Times](https://siliconanalysts.com/market-data/component-lead-times): CoWoS, HBM, wafer lead times 2022-2026.
- [Semiconductor Capex by Company](https://siliconanalysts.com/market-data/semiconductor-capex): TSMC, Samsung, Micron, SK Hynix, Intel annual capex 2022-2026.
- [NAND Flash Pricing](https://siliconanalysts.com/market-data/nand-flash-pricing): Enterprise and consumer SSD pricing, quarterly 2022-2026.
- [AI Server System BOM & Rack Cost](https://siliconanalysts.com/market-data/ai-server-system-bom): DGX H100 through GB200 NVL72 system-level costs.
- [AI Chip Cloud Spot Price](https://siliconanalysts.com/market-data/ai-chip-cloud-price): H100 and B200 hourly rental on CoreWeave, AWS, and spot markets.

### Market Data API
- GET /api/v1/market-data — List all 14 datasets with metadata (name, category, unit, description)
- GET /api/v1/market-data/{datasetId} — Data points for a dataset with source citations and confidence ratings

## Data Reference Pages
Structured, citable semiconductor cost data updated monthly. Ideal for sourcing specific numbers.

- [AI Chip Manufacturing Costs (2026)](https://siliconanalysts.com/data/ai-chip-costs): Manufacturing cost estimates for 8 leading AI accelerators — NVIDIA H100, H200, B200, GB200, AMD MI300X, MI325X, Intel Gaudi 2, Gaudi 3. Includes logic die cost, HBM cost, packaging cost, total manufacturing cost, sell price, and gross margin. H100 total BOM ~$3,320, GB200 ~$13,200.
- [Wafer Pricing by Process Node (2026)](https://siliconanalysts.com/data/wafer-pricing): TSMC and Samsung 300mm wafer pricing across nodes from 28nm ($3,000) to 3nm ($19,500). Includes NRE and mask set costs ($1.5M at 16nm to $15M at 3nm). Sourced from TrendForce, Morgan Stanley, CSET.
- [HBM Pricing and Specifications (2026)](https://siliconanalysts.com/data/hbm-pricing): HBM cost per stack and per GB across generations — HBM2e ($120/16GB), HBM3 ($200/24GB), HBM3E ($300/36GB), HBM4 ($500/48GB est.). Vendor market share (SK Hynix 50-55%, Samsung 35-40%, Micron 5-10%). Per-accelerator HBM cost allocations for H100, H200, B200, MI300X, MI325X.

## Semiconductor Cost Guides
- [Complete Semiconductor Cost Reference](https://siliconanalysts.com/guide/semiconductor-costs): Comprehensive guide covering wafer pricing by node, die cost economics, packaging costs (wire bond to CoWoS-L), HBM pricing trends, NRE/mask set costs, and end-to-end chip cost modeling. Includes embedded interactive calculator.
- [TSMC 3nm Chip Cost Guide (2026)](https://siliconanalysts.com/guide/tsmc-3nm-cost): Dedicated cost breakdown for TSMC N3/N3E. Wafer cost $19,500, mask set $15M, die cost from ~$20 (50mm²) to ~$800+ (814mm²). Includes yield estimates by die size, packaging and HBM cost additions, and total manufacturing cost examples for mobile SoC ($45–80), desktop GPU ($300–600), and AI accelerator ($3,000–13,000).
- [Chips Per Wafer Guide](https://siliconanalysts.com/guide/chips-per-wafer): How to calculate gross dies per wafer (GDPW) and net die yield. Includes GDPW formula, yield models (Murphy, Poisson), die size impact on cost, and reference table for IoT MCU (~2,800 GDPW), smartphone SoC (~580), laptop CPU (~340), and NVIDIA H100 (~80). Explains chiplet economics.
- [Foundry Engagement Guide](https://siliconanalysts.com/guide/foundry-engagement): Step-by-step guide from MPW shuttle ($5K-$100K) to production ($500K-$15M+ NRE). Covers 3 engagement models (MPW, VCA intermediary, direct foundry), 7-phase process (NDA → PDK → design → tapeout → fab → package → production), node selection (28nm to 3nm with cost/mask data), NRE cost tables, and foundry comparison (TSMC, Samsung, GlobalFoundries, Intel IFS, UMC, SMIC).

## Analysis Articles
Browse all: https://siliconanalysts.com/analysis

30+ deep-dive reports covering NVIDIA GPU pricing, TSMC capacity constraints, HBM supply chain dynamics, AMD market trajectory, Intel foundry strategy, semiconductor trade war impacts, advanced packaging technology, and AI chip demand forecasting.

### Featured Analysis
- [Chip Manufacturing Energy Costs & Emissions](https://siliconanalysts.com/analysis/chip-manufacturing-energy-cost): Interactive analysis with 6 charts covering semiconductor fab energy consumption and carbon emissions. HBM consumes 3–5× more manufacturing energy per GB than standard DRAM. Compares industrial electricity rates across 8 fab locations (Texas $0.061/kWh to Germany $0.183/kWh), renewable energy adoption by manufacturer (Intel 98% to TSMC 14%), energy intensity by process node (150 kWh at 130nm to 1,400 kWh at 2nm), CO₂ per wafer by grid mix, and industry electricity consumption forecast to 2030 (237 TWh BAU). Sources: ASML, imec, McKinsey, Greenpeace East Asia, company sustainability reports.
- [NVIDIA B200 Cost Breakdown](https://siliconanalysts.com/analysis/nvidia-b200-blackwell-cost-breakdown): NVIDIA B200 manufacturing cost breakdown — $6,400 COGS across dual-die logic, HBM3e, CoWoS-L packaging.

## Terms
https://siliconanalysts.com/terms